Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
1341
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
45.
Analog-Front-End Controller (AFEC)
45.1
Description
The Analog-Front-End Controller (AFEC) is based on a 12-bit Analog-to-Digital Converter (ADC) managed by an
AFE Controller. Refer to the Block Diagram:
AFE Controller. Refer to the Block Diagram:
. It also integrates a 16-to-1 analog multiplexer, making
possible the analog-to-digital conversions of 16 analog lines. The conversions extend from 0V to ADVREF. The
AFEC supports an 10-bit or 12-bit resolution mode which can be extended up to a 16-bit resolution by digital
averaging, and conversion results are reported in a common register for all channels, as well as in a channel-
dedicated register. Software trigger, external trigger on rising edge of the AFE_ADTRG pin or internal triggers from
Timer Counter output(s) are configurable.
AFEC supports an 10-bit or 12-bit resolution mode which can be extended up to a 16-bit resolution by digital
averaging, and conversion results are reported in a common register for all channels, as well as in a channel-
dedicated register. Software trigger, external trigger on rising edge of the AFE_ADTRG pin or internal triggers from
Timer Counter output(s) are configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a
given range or outside the range, thresholds and ranges being fully configurable.
given range or outside the range, thresholds and ranges being fully configurable.
The AFE Controller internal fault output is directly connected to PWM Fault input. This input can be asserted by
means of comparison circuitry in order to immediately put the PWM outputs in a safe state (pure combinational
path).
means of comparison circuitry in order to immediately put the PWM outputs in a safe state (pure combinational
path).
The AFEC also integrates a Sleep Mode and a conversion sequencer and connects with a PDC channel. These
features reduce both power consumption and processor intervention.
features reduce both power consumption and processor intervention.
This AFEC has a selectable single-ended or fully differential input and benefits from a 2-bit programmable gain. A
whole set of reference voltages is generated internally from a single external reference voltage node that may be
equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.
whole set of reference voltages is generated internally from a single external reference voltage node that may be
equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.
A digital error correction circuit based on the multi-bit redundant signed digit (RSD) algorithm is employed in order
to reduce INL and DNL errors.
to reduce INL and DNL errors.
Finally, the user can configure AFEC timings, such as startup time and tracking time.
45.2
Embedded Characteristics
12-bit resolution up to 16-bit resolution by digital averaging
1 MHz conversion rate
Wide range power supply operation
Selectable Single Ended or Differential input voltage
Programmable Gain for maximum full scale input range 0–V
DD
Programmable offset per channel
Integrated multiplexer offering up to 16 independent analog inputs
Individual enable and disable of each channel
Hardware or software trigger
̶
External trigger pin
̶
Timer counter outputs (corresponding TIOA trigger)
̶
PWM event line
Drive of PWM fault input
PDC support
Possibility of AFEC timings configuration
Two Sleep Modes and Conversion Sequencer
̶
Automatic Wake-up on Trigger and Back to Sleep Mode after conversions of all enabled channels
̶
Possibility of customized channel sequence
Standby Mode for Fast Wake-up time response
̶
Power-down Capability