Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

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SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

The DACC start-up time must be defined by the user in the STARTUP field of the DACC_MR.

A maximum speed mode is available by setting the MAXS bit in the DACC_MR. In this mode, the DACC no longer
waits to sample the end-of-cycle signal coming from the DACC block to start the next conversion. An internal
counter is used instead, thus gaining two peripheral clock periods between each consecutive conversion.

Warning: If the maximum speed mode is used, the EOC interrupt of the DACC_IER should not be used as it is two
peripheral clock periods late.

The accuracy of the analog voltage resulting from the data conversion process cannot be guaranteed due to
leakage. To ensure accuracy, the channel must be refreshed on a regular basis. A value is correctly refreshed if
the correct sampling period is selected (see DACC electrical characteristics) and the software or PDC is able to
sustain writing to DACC_CDR at the rate imposed by the trigger period. 

To prevent any single software error from corrupting DACC behavior, certain registers in the address space can be
write-protected by setting the WPEN bit in the 

 (DACC_WPMR).

If a write access to a write-protected register is detected, the WPVS flag in the 

 (DACC_WPSR) is set and the field WPVSRC indicates the register in which the write access has been

attempted.

The WPVS bit is automatically cleared after reading the DACC_WPSR.

The following registers can be write-protected:









Peripheral clock

Write USER_SEL 

field

Selected Channel

Write DACC_CDR

DAC Channel 0

Output

DAC Channel 1

Output

EOC

Read DACC_ISR

Select Channel 0

Channel 0

Channel 1

Data 0

Data 1

Data 2

Data 0

Data 1

Data 2

Select Channel 1

None

TXRDY

CDR FIFO not full