Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
219
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12.7
Cortex-M4 Core Peripherals
12.7.1 Peripherals
Nested Vectored Interrupt Controller (NVIC)
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interrupt processing. See
The Nested Vectored Interrupt Controller (NVIC) is an embedded interrupt controller that supports low
latency interrupt processing. See
System Control Block (SCB)
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See
The System Control Block (SCB) is the programmers model interface to the processor. It provides system
implementation information and system control, including configuration, control, and reporting of system
exceptions. See
System Timer (SysTick)
The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System
(RTOS) tick timer or as a simple counter. See
The System Timer, SysTick, is a 24-bit count-down timer. Use this as a Real Time Operating System
(RTOS) tick timer or as a simple counter. See
Memory Protection Unit (MPU)
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See
The Memory Protection Unit (MPU) improves system reliability by defining the memory attributes for different
memory regions. It provides up to eight different regions, and an optional predefined background region.
See
Floating-point Unit (FPU)
The Floating-point Unit (FPU) provides IEEE754-compliant operations on single-precision, 32-bit, floating-
point values. See
The Floating-point Unit (FPU) provides IEEE754-compliant operations on single-precision, 32-bit, floating-
point values. See
12.7.2 Address Map
The address map of the Private peripheral bus (PPB) is:
In register descriptions:
The required privilege gives the privilege level required to access the register, as follows:
̶
Privileged: Only privileged software can access the register.
̶
Unprivileged: Both unprivileged and privileged software can access the register.
Table 12-29.
Core Peripheral Register Regions
Address
Core Peripheral
0xE000E008–0xE000E00F
System Control Block
0xE000E010–0xE000E01F
System Timer
0xE000E100–0xE000E4EF
Nested Vectored Interrupt Controller
0xE000ED00–0xE000ED3F
System control block
0xE000ED90–0xE000EDB8
Memory Protection Unit
0xE000EF00–0xE000EF03
Nested Vectored Interrupt Controller
0xE000EF30–0xE000EF44
Floating-point Unit