Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
287
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
12.12 Floating Point Unit (FPU)
The Cortex-M4F FPU implements the FPv4-SP floating-point extension.
The FPU fully supports single-precision add, subtract, multiply, divide, multiply and accumulate, and square root
operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point
constant instructions.
operations. It also provides conversions between fixed-point and floating-point data formats, and floating-point
constant instructions.
The FPU provides floating-point computation functionality that is compliant with the ANSI/IEEE Std 754-2008,
IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.
IEEE Standard for Binary Floating-Point Arithmetic, referred to as the IEEE 754 standard.
The FPU contains 32 single-precision extension registers, which can also be accessed as 16 doubleword registers
for load, store, and move operations.
for load, store, and move operations.
12.12.1 Enabling the FPU
The FPU is disabled from reset. It must be enabled before any floating-point instructions can be used. Example 4-
1 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must
be in privileged mode to read from and write to the CPACR.
1 shows an example code sequence for enabling the FPU in both privileged and user modes. The processor must
be in privileged mode to read from and write to the CPACR.
Example of Enabling the FPU:
; CPACR is located at address 0xE000ED88
LDR.W R0, =0xE000ED88
; Read CPACR
LDR R1, [R0]
; Set bits 20-23 to enable CP10 and CP11 coprocessors
ORR R1, R1, #(0xF << 20)
; Write back the modified value to the CPACR
STR R1, [R0]; wait for store to complete
DSB
;reset pipeline now the FPU is enabled
ISB