Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
305
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
13.6
Functional Description
13.6.1 Test Pin
The TST pin is used for JTAG Boundary Scan Manufacturing Test or Fast Flash programming mode of the
SAM4E
series. The TST pin integrates a permanent pull-down resistor of about 15 k
Ω
to GND, so that it can be left uncon-
nected for normal operations. To enter fast programming mode, see the Fast Flash Programming Interface (FFPI)
section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product
datasheet.
section. For more on the manufacturing and test mode, refer to the “Debug and Test” section of the product
datasheet.
13.6.2 NRST Pin
The NRST pin is bidirectional. It is handled by the on-chip reset controller and can be driven low to provide a reset
signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and
the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length
of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a
permanent pull-up resistor to VDDIO of about 100 k
signal to the external components or asserted low externally to reset the microcontroller. It will reset the Core and
the peripherals except the Backup region (RTC, RTT and Supply Controller). There is no constraint on the length
of the reset pulse and the reset controller can guarantee a minimum pulse length. The NRST pin integrates a
permanent pull-up resistor to VDDIO of about 100 k
Ω. By default, the NRST pin is configured as an input.
13.6.3 ERASE Pin
The ERASE pin is used to reinitialize the Flash content (and some of its NVM bits) to an erased state (all bits read
as logic level 1). It integrates a pull-down resistor of about 100 k
as logic level 1). It integrates a pull-down resistor of about 100 k
Ω to GND, so that it can be left unconnected for
normal operations.
This pin is debounced by SCLK to improve the glitch tolerance. To avoid unexpected erase at power-up, a
minimum ERASE pin assertion time is required. This time is defined in
minimum ERASE pin assertion time is required. This time is defined in
The ERASE pin is a system I/O pin and can be used as a standard I/O. At startup, the ERASE pin is not configured
as a PIO pin. If the ERASE pin is used as a standard I/O, start-up level of this pin must be low to prevent unwanted
erasing. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash.
For details, please refer to the “Peripheral Signal Multiplexing on I/O Lines” section of this datasheet.
as a PIO pin. If the ERASE pin is used as a standard I/O, start-up level of this pin must be low to prevent unwanted
erasing. Also, if the ERASE pin is used as a standard I/O output, asserting the pin to low does not erase the Flash.
For details, please refer to the “Peripheral Signal Multiplexing on I/O Lines” section of this datasheet.
13.6.4 Debug Architecture
debug:
SWJ-DP (Serial Wire/JTAG Debug Port)
FPB (Flash Patch Breakpoint)
DWT (Data Watchpoint and Trace)
ITM (Instrumentation Trace Macrocell)
TPIU (Trace Port Interface Unit)
The debug architecture information that follows is mainly dedicated to developers of SWJ-DP Emulators/Probes
and debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the Cortex-
M4 technical reference manual.
and debugging tool vendors for Cortex-M4 based microcontrollers. For further details on SWJ-DP see the Cortex-
M4 technical reference manual.