Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
452
25.8.1.1 Undefined Length Burst Arbitration
In order to prevent long AHB burst lengths that can lock the access to the slave for an excessive period of time, the
user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be
selected from the following Undefined Length Burst Type (ULBT) possibilities:
user can trigger the re-arbitration before the end of the incremental bursts. The re-arbitration period can be
selected from the following Undefined Length Burst Type (ULBT) possibilities:
1.
Unlimited: no predetermined end of burst is generated. This value enables 1-Kbyte burst lengths.
2.
1-beat bursts: predetermined end of burst is generated at each single transfer during the INCR transfer.
3.
4-beat bursts: predetermined end of burst is generated at the end of each 4-beat boundary during INCR
transfer.
transfer.
4.
8-beat bursts: predetermined end of burst is generated at the end of each 8-beat boundary during INCR
transfer.
transfer.
5.
16-beat bursts: predetermined end of burst is generated at the end of each 16-beat boundary during INCR
transfer.
transfer.
6.
32-beat bursts: predetermined end of burst is generated at the end of each 32-beat boundary during INCR
transfer.
transfer.
7.
64-beat bursts: predetermined end of burst is generated at the end of each 64-beat boundary during INCR
transfer.
transfer.
8.
128-beat bursts: predetermined end of burst is generated at the end of each 128-beat boundary during INCR
transfer.
transfer.
The use of undefined length16-beat bursts, or less, is discouraged since this generally decreases significantly the
overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.
overall bus bandwidth due to arbitration and slave latencies at each first access of a burst.
If the master does not permanently and continuously request the same slave or has an intrinsically limited average
throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits
all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kilobyte address boundaries.
throughput, the ULBT should be left at its default unlimited value, knowing that the AHB specification natively limits
all word bursts to 256 beats and double-word bursts to 128 beats because of its 1 Kilobyte address boundaries.
Unless duly needed, the ULBT should be left at its default value of 0 for power saving.
This selection can be done through the ULBT field of the Master Configuration Registers (MATRIX_MCFG).
25.8.1.2 Slot Cycle Limit Arbitration
The Bus Matrix contains specific logic to break long accesses, such as very long bursts on a very slow slave (e.g.,
an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in
the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock
cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access
cycle.
an external low speed memory). At each arbitration time, a counter is loaded with the value previously written in
the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock
cycle. When the counter elapses, the arbiter has the ability to re-arbitrate at the end of the current AHB bus access
cycle.
Unless a master has a very tight access latency constraint, which could lead to data overflow or underflow due to a
badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled
(SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by
some Atmel masters.
badly undersized internal FIFO with respect to its throughput, the Slot Cycle Limit should be disabled
(SLOT_CYCLE = 0) or set to its default maximum value in order not to inefficiently break long bursts performed by
some Atmel masters.
In most cases, this feature is not needed and should be disabled for power saving.
Warning: This feature cannot prevent any slave from locking its access indefinitely.
25.8.2 Arbitration Priority Scheme
The bus Matrix arbitration scheme is organized in priority pools.
Round-robin priority is used in the highest and lowest priority pools, whereas fixed level priority is used between
priority pools and in the intermediate priority pools.
priority pools and in the intermediate priority pools.
For each slave, each master is assigned to one of the slave priority pools through the priority registers for slaves
(MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority
level always takes precedence.
(MxPR fields of MATRIX_PRAS and MATRIX_PRBS). When evaluating master requests, this programmed priority
level always takes precedence.