Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet

SAM4E [DATASHEET]

Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14

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All multi-buffer transfers must end as shown in Row 1 of 

. At the end of every buffer transfer, the DMAC

samples the row number, and if the DMAC is in Row 1 state, then the previous buffer transferred was the last
buffer and the DMAC transfer is terminated. 

For rows 2, 3, 4, 5, and 6 (DMAC_CRTLBx.AUTO cleared), the user must set up the last buffer descriptor in
memory so that LLI.DMAC_DSCRx is set to 0.

Four registers, the DMAC_DSCRx, the DMAC_CTRLAx, the DMAC_CTRLBx and DMAC_CFGx, need to be
programmed to set up whether single or multi-buffer transfers take place, and which type of multi-buffer transfer is
used. The different transfer types are shown in 

.

The “BTSIZE, SADDR and DADDR” columns indicate where the values of DMAC_SARx, DMAC_DARx,
DMAC_CTLx, and DMAC_LLPx are obtained for the next buffer transfer when multi-buffer DMAC transfers are
enabled.

1.

Read the Channel Handler Status Register DMAC_CHSR.ENAx Field to choose a free (disabled) channel.

2.

Clear any pending interrupts on the channel from the previous DMAC transfer by reading the interrupt status 
register, DMAC_EBCISR.

3.

Program the following channel registers:

1.

Write the starting source address in the DMAC_SADDRx register for channel x.

2.

Write the starting destination address in the DMAC_DADDRx register for channel x.

3.

Write the next descriptor address in the DMA_DSCRx register for channel x with 0x0.

4.

Program DMAC_CTRLAx, DMAC_CTRLBx and DMAC_CFGx according to Row 1 as shown in 

5.

Write the control information for the DMAC transfer in the DMAC_CTRLAx and DMAC_CTRLBx registers 
for channel x. For example, in the register, you can program the following:

̶

i. Set up the transfer type (memory or non-memory peripheral for source and destination) and flow 
control device by programming the FC of the DMAC_CTRLBx register.

̶

ii. Set up the transfer characteristics, such as:



Transfer width for the source in the SRC_WIDTH field.



Transfer width for the destination in the DST_WIDTH field.



Incrementing/decrementing or fixed address for source in SRC_INC field.



Incrementing/decrementing or fixed address for destination in DST_INC field.

6.

Write the channel configuration information into the DMAC_CFGx register for channel x.

̶

i. Designate the handshaking interface type (hardware or software) for the source and destination 
peripherals. This is not required for memory. This step requires programming the 
SRC_H2SEL/DST_H2SEL bits, respectively. Writing a ‘1’ activates the hardware handshaking 
interface to handle source/destination requests. Writing a ‘0’ activates the software handshaking 
interface to handle source/destination requests.

̶

ii. If the hardware handshaking interface is activated for the source or destination peripheral, assign a 
handshaking interface to the source and destination peripheral. This requires programming the 
SRC_PER and DST_PER bits, respectively.

4.

After the DMAC selected channel has been programmed, enable the channel by writing a ‘1’ to the 
DMAC_CHER.ENAx bit, where x is the channel number. Make sure that bit 0 of DMAC_EN.ENABLE 
register is enabled.