Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
551
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
28.12.3 Ready Mode
In Ready mode (EXNW_MODE = 11), the SMC behaves differently. Normally, the SMC begins the access by
down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse
phase, the resynchronized NWAIT signal is examined.
down counting the setup and pulse counters of the read/write controlling signal. In the last cycle of the pulse
phase, the resynchronized NWAIT signal is examined.
If asserted, the SMC suspends the access as shown in
. After deassertion, the
access is completed: the hold step of the access is performed.
This mode must be selected when the external device uses deassertion of the NWAIT signal to indicate its ability
to complete the read or write operation.
to complete the read or write operation.
If the NWAIT signal is deasserted before the end of the pulse, or asserted after the end of the pulse of the
controlling read/write signal, it has no impact on the access length as shown in
controlling read/write signal, it has no impact on the access length as shown in
.
Figure 28-25. NWAIT Assertion in Write Access: Ready Mode (EXNW_MODE = 11)
EXNW_MODE = 11 (Ready mode)
WRITE_MODE = 1 (NWE_controlled)
WRITE_MODE = 1 (NWE_controlled)
NWE_PULSE = 5
NCS_WR_PULSE = 7
NCS_WR_PULSE = 7
A[23:0]
MCK
NWE
NCS
4
3
2
1
0
0
0
4
5
6
3
2
1
1
1
0
Write cycle
D[7:0]
NWAIT
internally synchronized
NWAIT signal
Wait STATE