Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
591
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
It takes 2 slow RC oscillator clock cycles to detect and switch from the main oscillator, to the fast RC oscillator if
the source master clock (MCK) is main clock (MAINCK), or three slow clock RC oscillator cycles if the source of
MCK is PLLACK.
the source master clock (MCK) is main clock (MAINCK), or three slow clock RC oscillator cycles if the source of
MCK is PLLACK.
A clock failure detection activates a fault output that is connected to the Pulse Width Modulator (PWM) Controller.
With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock
failure is detected.
With this connection, the PWM controller is able to force its outputs and to protect the driven device, if a clock
failure is detected.
The user can know the status of the clock failure detector at any time by reading the FOS bit in PMC_SR.
This fault output remains active until the defect is detected and until it is cleared by the bit FOCLR in the PMC Fault
Output Clear Register (PMC_FOCR).
Output Clear Register (PMC_FOCR).
30.14 Programming Sequence
1.
If the fast crystal oscillator is not required, the PLL and divider can be directly configured (
) else the fast
crystal oscillator must be started (
).
2.
Enable the fast crystal oscillator:
The fast crystal oscillator is enabled by setting the MOSCXTEN field in CKGR_MOR. The user can define a
start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this
register has been correctly configured, the user must wait for MOSCXTS field in PMC_SR to be set. This
can be done either by polling MOSCXTS in PMC_SR, or by waiting for the interrupt line to be raised if the
associated interrupt source (MOSCXTS) has been enabled in PMC_IER.
start-up time. This can be achieved by writing a value in the MOSCXTST field in CKGR_MOR. Once this
register has been correctly configured, the user must wait for MOSCXTS field in PMC_SR to be set. This
can be done either by polling MOSCXTS in PMC_SR, or by waiting for the interrupt line to be raised if the
associated interrupt source (MOSCXTS) has been enabled in PMC_IER.
3.
Switch the MAINCK to the main crystal oscillator by setting MOSCSEL in CKGR_MOR.
4.
Wait for the MOSCSELS to be set in PMC_SR to ensure the switchover is complete.
5.
Check the main clock frequency:
This main clock frequency can be measured via CKGR_MCFR.
Read CKGR_MCFR until the MAINFRDY field is set, after which the user can read the MAINF field in
CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have
been counted during a period of 16 slow clock cycles.
CKGR_MCFR by performing an additional read. This provides the number of main clock cycles that have
been counted during a period of 16 slow clock cycles.
If MAINF = 0, switch the MAINCK to the Fast RC Oscillator by clearing MOSCSEL in CKGR_MOR. If MAINF
≠ 0, proceed to
6.
Set PLLx and Divider (if not required, proceed to
):
In the names PLLx, DIVx, MULx, LOCKx, PLLxCOUNT, and CKGR_PLLxR, ‘x’ represents A.
All parameters needed to configure PLLx and the divider are located in CKGR_PLLxR.
The DIVx field is used to control the divider itself. This parameter can be programmed between 0 and 127.
Divider output is divider input divided by DIVx parameter. By default, DIVx field is set to 0 which means that
the divider and PLLx are turned off.
Divider output is divider input divided by DIVx parameter. By default, DIVx field is set to 0 which means that
the divider and PLLx are turned off.
The MULx field is the PLLx multiplier factor. This parameter can be programmed between 0 and 80. If MULx
is set to 0, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by
(MULx + 1).
is set to 0, PLLx will be turned off, otherwise the PLLx output frequency is PLLx input frequency multiplied by
(MULx + 1).
The PLLxCOUNT field specifies the number of slow clock cycles before the LOCKx bit is set in the PMC_SR
after CKGR_PLLxR has been written.
after CKGR_PLLxR has been written.
Once CKGR_PLLxR has been written, the user must wait for the LOCKx bit to be set in the PMC_SR. This
can be done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be
programmed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is
modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set
again. The user must wait for the LOCKx bit to be set before using the PLLx output clock.
can be done either by polling LOCKx in PMC_SR or by waiting for the interrupt line to be raised if the
associated interrupt source (LOCKx) has been enabled in PMC_IER. All fields in CKGR_PLLxR can be
programmed in a single write operation. If at some stage one of the following parameters, MULx or DIVx is
modified, the LOCKx bit goes low to indicate that PLLx is not yet ready. When PLLx is locked, LOCKx is set
again. The user must wait for the LOCKx bit to be set before using the PLLx output clock.