Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
660
33.7.3 Time Management Unit
The CAN Controller integrates a free-running 16-bit internal timer. The counter is driven by the bit clock of the CAN
bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR). It is automatically cleared
in the following cases:
bus line. It is enabled when the CAN controller is enabled (CANEN set in the CAN_MR). It is automatically cleared
in the following cases:
after a reset
when the CAN controller is in Low-power Mode is enabled (LPM bit set in the CAN_MR and SLEEP bit set in
the CAN_SR)
the CAN_SR)
after a reset of the CAN controller (CANEN bit in the CAN_MR)
in Time-triggered Mode, when a message is accepted by the last mailbox (rising edge of the MRDY signal in
the CAN_MSR
the CAN_MSR
last_mailbox_number
register).
The application can also reset the internal timer by setting TIMRST in the CAN_TCR. The current value of the
internal timer is always accessible by reading the CAN_TIM register.
internal timer is always accessible by reading the CAN_TIM register.
When the timer rolls-over from FFFFh to 0000h, TOVF (Timer Overflow) signal in the CAN_SR is set. TOVF bit in
the CAN_SR is cleared by reading the CAN_SR. Depending on the corresponding interrupt mask in the CAN_IMR,
an interrupt is generated while TOVF is set.
the CAN_SR is cleared by reading the CAN_SR. Depending on the corresponding interrupt mask in the CAN_IMR,
an interrupt is generated while TOVF is set.
In a CAN network, some CAN devices may have a larger counter. In this case, the application can also decide to
freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device.
This feature is enabled by setting TIMFRZ in the CAN_MR. The CAN_TIM register is frozen to the FFFFh value. A
clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.
freeze the internal counter when the timer reaches FFFFh and to wait for a restart condition from another device.
This feature is enabled by setting TIMFRZ in the CAN_MR. The CAN_TIM register is frozen to the FFFFh value. A
clear condition described above restarts the timer. A timer overflow (TOVF) interrupt is triggered.
To monitor the CAN bus activity, the CAN_TIM register is copied to the CAN _TIMESTP register after each start of
frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR is set, the value is captured at
each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the
CAN_IMR, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the
CAN_SR.
frame or end of frame and a TSTP interrupt is triggered. If TEOF bit in the CAN_MR is set, the value is captured at
each End Of Frame, else it is captured at each Start Of Frame. Depending on the corresponding mask in the
CAN_IMR, an interrupt is generated while TSTP is set in the CAN_SR. TSTP bit is cleared by reading the
CAN_SR.
The time management unit can operate in one of the two following modes:
Timestamping mode: The value of the internal timer is captured at each Start Of Frame or each End Of
Frame
Frame
Time Triggered mode: A mailbox transfer operation is triggered when the internal timer reaches the mailbox
trigger.
trigger.
Timestamping Mode is enabled by clearing TTM field in the CAN_MR. Time Triggered Mode is enabled by setting
TTM field in the CAN_MR.
TTM field in the CAN_MR.
33.7.4 CAN 2.0 Standard Features
33.7.4.1 CAN Bit Timing Configuration
All controllers on a CAN bus must have the same bit rate and bit length. At different clock frequencies of the
individual controllers, the bit rate has to be adjusted by the time segments.
individual controllers, the bit rate has to be adjusted by the time segments.
The CAN protocol specification partitions the nominal bit time into four different segments.