Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
801
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
When operating with decoding, the SPI directly outputs the value defined by the PCS field on the NPCS lines of
either SPI_MR or SPI_TDR (depending on PS).
either SPI_MR or SPI_TDR (depending on PS).
As the SPI sets a default value of 0xF on the chip select lines (i.e., all chip select lines at 1) when not processing
any transfer, only 15 peripherals can be decoded.
any transfer, only 15 peripherals can be decoded.
The SPI has four Chip Select registers. As a result, when external decoding is activated, each NPCS chip select
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Consequently, the user has to
make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
defines the characteristics of up to four peripherals. As an example, SPI_CRS0 defines the characteristics of the
externally decoded peripherals 0 to 3, corresponding to the PCS values 0x0 to 0x3. Consequently, the user has to
make sure to connect compatible peripherals on the decoded chip select lines 0 to 3, 4 to 7, 8 to 11 and 12 to 14.
shows this type of implementation.
If the CSAAT bit is used, with or without the PDC, the Mode Fault detection for NPCS0 line must be disabled. This
is not required for all other chip select lines since mode fault detection is only on NPCS0.
is not required for all other chip select lines since mode fault detection is only on NPCS0.
If the CSAAT bit is used, with or without the DMAC, the Mode Fault detection for NPCS0 line must be disabled.
This is not needed for all other chip select lines since mode fault detection is only on NPCS0.
This is not needed for all other chip select lines since mode fault detection is only on NPCS0.
Figure 35-10. Chip Select Decoding Application Block Diagram: Single Master/Multiple Slave Implementation
35.7.3.9 Peripheral Deselection without DMA nor PDC
During a transfer of more than one data on a Chip Select without the DMA nor PDC, the SPI_TDR is loaded by the
processor, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal Shift register.
When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between
consecutive transfers) in the SPI_CSR, will give even less time for the processor to reload the SPI_TDR. With
some SPI slave peripherals, if the chip select line must remain active (low) during a full set of transfers,
communication errors can occur.
processor, the TDRE flag rises as soon as the content of the SPI_TDR is transferred into the internal Shift register.
When this flag is detected high, the SPI_TDR can be reloaded. If this reload by the processor occurs before the
end of the current transfer and if the next transfer is performed on the same chip select as the current transfer, the
Chip Select is not de-asserted between the two transfers. But depending on the application software handling the
SPI status register flags (by interrupt or polling method) or servicing other interrupts or other tasks, the processor
may not reload the SPI_TDR in time to keep the chip select active (low). A null DLYBCT value (delay between
consecutive transfers) in the SPI_CSR, will give even less time for the processor to reload the SPI_TDR. With
some SPI slave peripherals, if the chip select line must remain active (low) during a full set of transfers,
communication errors can occur.
To facilitate interfacing with such devices, the Chip Select registers [CSR0...CSR3] can be programmed with the
Chip Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state
(low = active) until a transfer to another chip select is required. Even if the SPI_TDR is not reloaded, the chip select
Chip Select Active After Transfer (CSAAT) bit to 1. This allows the chip select lines to remain in their current state
(low = active) until a transfer to another chip select is required. Even if the SPI_TDR is not reloaded, the chip select
SPI Master
SPCK
MISO
MOSI
NPCS0
NPCS1
NPCS2
SPCK MISO MOSI
NSS
Slave 0
SPCK MISO MOSI
NSS
Slave 1
SPCK MISO MOSI
NSS
Slave 14
NPCS3
Decoded chip select lines
External 1-of-n Decoder/Demultiplexer