Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
828
Figure 36-8.
Master Write with One Byte Internal Address and Multiple Data Bytes
36.7.3.5 Master Receiver Mode
The read sequence begins by setting the START bit. After the start condition has been sent, the master sends a 7-
bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction—1
in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the
data line during this clock pulse and sets the NACK bit in the TWI_SR if the slave does not acknowledge the byte.
bit slave address to notify the slave device. The bit following the slave address indicates the transfer direction—1
in this case (MREAD = 1 in TWI_MMR). During the acknowledge clock pulse (9th pulse), the master releases the
data line (HIGH), enabling the slave to pull it down in order to generate the acknowledge. The master polls the
data line during this clock pulse and sets the NACK bit in the TWI_SR if the slave does not acknowledge the byte.
If an acknowledge is received, the master is then ready to receive data from the slave. After data has been
received, the master sends an acknowledge condition to notify the slave that the data has been received except
for the last data. See
received, the master sends an acknowledge condition to notify the slave that the data has been received except
for the last data. See
. When the RXRDY bit is set in the TWI_SR, a character has been received in the
Receive Holding Register (TWI_RHR). The RXRDY bit is reset when reading the TWI_RHR.
RXRDY is used as Receive Ready for the PDC receive channel.
When a single data byte read is performed, with or without internal address (IADR), the START and STOP bits
must be set at the same time. See
must be set at the same time. See
. When a multiple data byte read is performed, with or without
internal address (IADR), the STOP bit must be set after the next-to-last data received. See
Internal Address usage see
If the Receive Holding Register (TWI_RHR) is full (RXRDY high) and the master is receiving data, the Serial Clock
Line will be tied low before receiving the last bit of the data and until the TWI_RHR is read. Once the TWI_RHR is
read, the master will stop stretching the Serial Clock Line and end the data reception. See
Line will be tied low before receiving the last bit of the data and until the TWI_RHR is read. Once the TWI_RHR is
read, the master will stop stretching the Serial Clock Line and end the data reception. See
.
Warning: When receiving multiple bytes in master read mode, if the next-to-last access is not read (the RXRDY
flag remains high), the last access will not be completed until TWI_RHR is read. The last access stops on the next-
to-last bit (clock stretching). When the TWI_RHR is read there is only half a bit period to send the stop bit
command, else another read access might occur (spurious access).
flag remains high), the last access will not be completed until TWI_RHR is read. The last access stops on the next-
to-last bit (clock stretching). When the TWI_RHR is read there is only half a bit period to send the stop bit
command, else another read access might occur (spurious access).
A possible workaround is to set the STOP bit before reading the TWI_RHR on the next-to-last access (within IT
handler).
handler).
A
DATA n
A
S
DADR
W
DATA n+1
A
P
DATA n+2
A
TXCOMP
TXRDY
Write THR (Data n)
Write THR (Data n+1)
Write THR (Data n+2)
Last data sent
STOP command performed
(by writing in the TWI_CR)
TWD
IADR
A
TWCK