Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
831
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
1.
Program IADRSZ = 1,
2.
Program DADR with 1 1 1 1 0 b1 b2 (b1 is the MSB of the 10-bit address, b2, etc.)
3.
Program TWI_IADR with b3 b4 b5 b6 b7 b8 b9 b10 (b10 is the LSB of the 10-bit address)
below shows a byte write to an Atmel AT24LC512 EEPROM. This demonstrates the use of internal
addresses to access the device.
Figure 36-14. Internal Address Usage
36.7.3.7 Using the Peripheral DMA Controller (PDC)
The use of the PDC significantly reduces the CPU load.
To assure correct implementation, respect the following programming sequences:
Data Transmit with the PDC
1.
Initialize the transmit PDC (memory pointers, transfer size - 1).
2.
Configure the master (DADR, CKDIV, MREAD = 0, etc.)
3.
Start the transfer by setting the PDC TXTEN bit.
4.
Wait for the PDC ENDTX Flag either by using the polling method or ENDTX interrupt.
5.
Disable the PDC by setting the PDC TXTDIS bit.
6.
Wait for the TXRDY flag in TWI_SR.
7.
Set the STOP bit in TWI_CR.
8.
Write the last character in TWI_THR.
9.
(Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
Data Receive with the PDC
The PDC transfer size must be defined with the buffer size minus 2. The two remaining characters must be
managed without PDC to ensure that the exact number of bytes are received whatever the system bus latency
conditions encountered during the end of buffer transfer period.
managed without PDC to ensure that the exact number of bytes are received whatever the system bus latency
conditions encountered during the end of buffer transfer period.
In slave mode, the number of characters to receive must be known in order to configure the PDC.
1.
Initialize the receive PDC (memory pointers, transfer size - 2).
2.
Configure the master (DADR, CKDIV, MREAD = 1, etc.)
3.
Set the PDC RXTEN bit.
4.
(Master Only) Write the START bit in the TWI_CR to start the transfer.
5.
Wait for the PDC ENDRX Flag either by using polling method or ENDRX interrupt.
6.
Disable the PDC by setting the PDC RXTDIS bit.
7.
Wait for the RXRDY flag in TWI_SR.
8.
Set the STOP bit in TWI_CR.
9.
Read the penultimate character in TWI_RHR.
10. Wait for the RXRDY flag in TWI_SR.
11. Read the last character in TWI_RHR.
12. (Optional) Wait for the TXCOMP flag in TWI_SR before disabling the peripheral clock if required.
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Device
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FIRST
WORD ADDRESS
SECOND
WORD ADDRESS
DATA
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