Atmel Xplained Pro Evaluation Kit ATSAM4E-XPRO ATSAM4E-XPRO Data Sheet
Product codes
ATSAM4E-XPRO
855
SAM4E [DATASHEET]
Atmel-11157D-ATARM-SAM4E16-SAM4E8-Datasheet_12-Jun-14
36.8.5 TWI Clock Waveform Generator Register
Name: TWI_CWGR
Address:
0x400A8010 (0), 0x400AC010 (1)
Access: Read/Write
Reset:
0x00000000
This register can only be written if the WPEN bit is cleared in the
TWI_CWGR is only used in Master mode.
CLDIV: Clock Low Divider
The SCL low period is defined as follows: t
low
= ((CLDIV
× 2
CKDIV
) + 4
× t
peripheral clock
CHDIV: Clock High Divider
The SCL high period is defined as follows: t
high
= ((CHDIV
× 2
CKDIV
) + 4
× t
peripheral clock
CKDIV: Clock Divider
The CKDIV is used to increase both SCL high and low periods.
31
30
29
28
27
26
25
24
–
–
–
–
–
–
–
–
23
22
21
20
19
18
17
16
–
–
–
–
–
CKDIV
15
14
13
12
11
10
9
8
CHDIV
7
6
5
4
3
2
1
0
CLDIV