Atmel ARM-Based Evaluation Kit AT91SAM9N12-EK AT91SAM9N12-EK Data Sheet

 11063K–ATARM–05-Nov-13

Based on the ARM926EJ-S

™

 processor, the Atmel

®

 SAM9N12/CN11/CN12 devices

offer the frequently-requested combination of user interface functionality and high data
rate connectivity, with LCD Controller, resistive touch-screen, multiple UARTs, SPI,
I2C, full-speed USB Host and Device and SDIO.

The SAM9N12/CN11/CN12 support the latest generation of LPDDR/DDR2 and NAND
Flash memory interfaces for program and data storage. An internal 133 MHz multi-
layer bus architecture associated with eight DMA channels and distributed memory –
including a 32-Kbyte SRAM – sustains the high bandwidth required by the processor
and the high-speed peripherals.

The SAM9CN11/CN12 offer on-chip hardware accelerators with DMA support that
enable high-speed data encryption and authentication of transferred data or applica-
tions. Supported standards are up to 256-bit AES, and FIPS Publication 180-2
compliant SHA1 and SHA256. A True Random Number Generator is embedded for
key generation and exchange protocols. The devices also feature fuse bits for crypto
key (SAM9CN12), user configuration (SAM9N12 and SAM9CN11) and device configu-
ration (all). The SAM9CN12 includes a secured Boot ROM; the SAM9N12 and
SAM9CN11 include a standard Boot ROM.

The I/Os support 1.8V or 3.3V operation and are independently configurable for
the memory interface and peripheral I/Os. This feature eliminates the need for any
external level shifters, while 0.8 ball pitch packages lower PCB cost and complexity.

The SAM9N12/CN11/CN12 power management controllers feature efficient clock gat-
ing and a battery backup section that minimizes power consumption in active and
standby modes. There are several devices. The table that follows presents the embed-
ded features of each device.

Standard Boot with BSC

X

X

–

Secured Boot

–

–

X

TRNG

X

X

X

AES

–

X

X

SHA

–

X

X