Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

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SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

The EMAC module implements a 10/100 Ethernet MAC compatible with the IEEE 802.3 standard using an address 
checker, statistics and control registers, receive and transmit blocks, and a DMA interface.

The address checker recognizes four specific 48-bit addresses and contains a 64-bit hash register for matching multicast 
and unicast addresses. It can recognize the broadcast address of all ones, copy all frames, and act on an external 
address match signal.

The statistics register block contains registers for counting various types of event associated with transmit and receive 
operations. These registers, along with the status words stored in the receive buffer list, enable software to generate 
network management statistics compatible with IEEE 802.3.

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EMAC0 supports MII and RMII interfaces to the physical layer (EMAC1 supports RMII only)

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Compatible with IEEE Standard 802.3

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10 and 100 Mbit/s Operation

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Full-duplex and Half-duplex Operation

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Statistics Counter Registers

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Interrupt Generation to Signal Receive and Transmit Completion

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DMA Master on Receive and Transmit Channels

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Transmit and Receive FIFOs

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Automatic Pad and CRC Generation on Transmitted Frames

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Automatic Discard of Frames Received with Errors

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Address Checking Logic Supports Up to Four Specific 48-bit Addresses

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Supports Promiscuous Mode Where All Valid Received Frames are Copied to Memory

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Hash Matching of Unicast and Multicast Destination Addresses

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Physical Layer Management through MDIO Interface

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Half-duplex Flow Control by Forcing Collisions on Incoming Frames

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Full-duplex Flow Control with Recognition of Incoming Pause Frames 

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Support for 802.1Q VLAN Tagging with Recognition of Incoming VLAN and 

Priority Tagged Frames

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Multiple Buffers per Receive and Transmit Frame

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Jumbo Frames Up to 10240 bytes Supported