Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
1026
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
45.4.2.1 FIFO
The FIFO depths are 1
28
bytes for receive and 1
28
bytes for transmit and are a function of the system clock speed,
memory latency and network speed.
Data is typically transferred into and out of the FIFOs in bursts of four words. For receive, a bus request is asserted when
the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space
for four words, or when there is space for 27 words if the next transfer is to be only one or two words.
the FIFO contains four words and has space for 28 more. For transmit, a bus request is generated when there is space
for four words, or when there is space for 27 words if the next transfer is to be only one or two words.
Thus the bus latency must be less than the time it takes to load the FIFO and transmit or receive three words (112 bytes)
of data.
of data.
At 100 Mbit/s, it takes 8960 ns to transmit or receive 112 bytes of data. In addition, six master clock cycles should be
allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 133 MHz master clock this takes
45 ns, making the bus latency requirement 8915 ns.
allowed for data to be loaded from the bus and to propagate through the FIFOs. For a 133 MHz master clock this takes
45 ns, making the bus latency requirement 8915 ns.
45.4.2.2 Receive Buffers
Received frames, including CRC/FCS optionally, are written to receive buffers stored in memory. Each receive buffer is
128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a
location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For
the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14
and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer
of a frame is reduced by the corresponding number of bytes.
128 bytes long. The start location for each receive buffer is stored in memory in a list of receive buffer descriptors at a
location pointed to by the receive buffer queue pointer register. The receive buffer start location is a word address. For
the first buffer of a frame, the start location can be offset by up to three bytes depending on the value written to bits 14
and 15 of the network configuration register. If the start location of the buffer is offset the available length of the first buffer
of a frame is reduced by the corresponding number of bytes.
Each list entry consists of two words, the first being the address of the receive buffer and the second being the receive
status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes
except for the “start of frame” bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show
the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with
receive frame data. The final buffer descriptor status word contains the complete frame status. Refer to
status. If the length of a receive frame exceeds the buffer length, the status word for the used buffer is written with zeroes
except for the “start of frame” bit and the offset bits, if appropriate. Bit zero of the address field is written to one to show
the buffer has been used. The receive buffer manager then reads the location of the next receive buffer and fills that with
receive frame data. The final buffer descriptor status word contains the complete frame status. Refer to
details of the receive buffer descriptor list.
Table 45-1. Receive Buffer Descriptor Entry
Bit
Function
Word 0
31:2
Address of beginning of buffer
1
Wrap - marks last descriptor in receive buffer descriptor list.
0
Ownership - needs to be zero for the EMAC to write data to the receive buffer. The EMAC sets this to one once it has
successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
successfully written a frame to memory.
Software has to clear this bit before the buffer can be used again.
Word 1
31
Global all ones broadcast address detected
30
Multicast hash match
29
Unicast hash match
28
External address match
27
Reserved for future use
26
Specific address register 1 match
25
Specific address register 2 match
24
Specific address register 3 match
23
Specific address register 4 match
22
Type ID match