Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
1033
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
The following bits in the receive buffer descriptor status word give information about VLAN tagged frames:
Bit 21 set if receive frame is VLAN tagged (i.e. type id of 0x8100)
Bit 20 set if receive frame is priority tagged (i.e. type id of 0x8100 and null VID). (If bit 20 is set bit 21 is set also.)
Bit 19, 18 and 17 set to priority if bit 21 is set
Bit 16 set to CFI if bit 21 is set
45.4.12 PHY Maintenance
The register EMAC_MAN enables the EMAC to communicate with a PHY by means of the MDIO interface. It is used
during auto-negotiation to ensure that the EMAC and the PHY are configured for the
during auto-negotiation to ensure that the EMAC and the PHY are configured for the
same speed and duplex
configuration.
The PHY maintenance register is implemented as a shift register. Writing to the register starts a shift operation which is
signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set
to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
signalled as complete when bit two is set in the network status register (about 2000 MCK cycles later when bit ten is set
to zero, and bit eleven is set to one in the network configuration register). An interrupt is generated as this bit is set.
During this time, the MSB of the register is output on the MDIO pin and the LSB updated from the MDIO pin with each
MDC cycle. This causes transmission of a PHY management frame on MDIO.
Reading during the shift operation returns the current contents of the shift register. At the end of management operation,
the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from
the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
the bits have shifted back to their original locations. For a read operation, the data bits are updated with data read from
the PHY. It is important to write the correct values to the register to ensure a valid PHY management frame is produced.
The MDIO interface can read IEEE 802.3 clause 45 PHYs as well as clause 22 PHYs. To read clause 45 PHYs,
bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in
the
bits[31:28] should be written as 0x0011. For a description of MDC generation, see the network configuration register in
the
45.4.13 Physical Interface
Depending on products, the Ethernet MAC is capable of interfacing to RMII or MII Interface. The RMII bit in the
EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the
MII interface is selected.
EMAC_USRIO register controls the interface that is selected. When this bit is set, the RMII interface is selected, else the
MII interface is selected.
The MII and RMII interfaces are capable of both 10 Mb/s and 100 Mb/s data rates as described in the IEEE 802.3u
standard. The signals used by the MII and RMII interfaces are described in
standard. The signals used by the MII and RMII interfaces are described in
The intent of the RMII is to provide a reduced pin count alternative to the IEEE 802.3u MII. It uses two bits for transmit
(ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error
(ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100 Mb/s data rate.
(ETX0 and ETX1) and two bits for receive (ERX0 and ERX1). There is a Transmit Enable (ETXEN), a Receive Error
(ERXER), a Carrier Sense (ECRS_DV), and a 50 MHz Reference Clock (ETXCK_EREFCK) for 100 Mb/s data rate.
Table 45-5. Pin Configuration
Pin Name
MII
RMII
ETXCK_EREFCK
ETXCK: Transmit Clock
EREFCK: Reference Clock
ECRS
ECRS: Carrier Sense
–
ECOL
ECOL: Collision Detect
–
ERXDV
ERXDV: Data Valid
ECRSDV: Carrier Sense/Data Valid
ERX0–ERX3
ERX0–ERX3: 4-bit Receive Data
ERX0–ERX1: 2-bit Receive Data
ERXER
ERXER: Receive Error
ERXER: Receive Error
ERXCK
ERXCK: Receive Clock
–
ETXEN
ETXEN: Transmit Enable
ETXEN: Transmit Enable
ETX0–ETX3
ETX0–ETX3: 4-bit Transmit Data
ETX0–ETX1: 2-bit Transmit Data
ETXER
ETXER: Transmit Error
–