Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
106
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
14.4 Functional Description
14.4.1 Reset Controller Overview
The Reset Controller is made up of an NRST Manager, a Startup Counter and a Reset State Manager. It runs at Slow
Clock and generates the following reset signals:
Clock and generates the following reset signals:
proc_nreset: Processor reset line. It also resets the Watchdog Timer.
backup_nreset: Affects all the peripherals powered by VDDBU.
periph_nreset: Affects the whole set of embedded peripherals.
nrst_out: Drives the NRST pin.
These reset signals are asserted by the Reset Controller, either on external events or on software action. The Reset
State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of
the NRST pin is required.
State Manager controls the generation of reset signals and provides a signal to the NRST Manager when an assertion of
the NRST pin is required.
The NRST Manager shapes the NRST assertion during a programmable time, thus controlling external device resets.
The startup counter waits for the complete crystal oscillator startup. The wait delay is given by the crystal oscillator
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
startup time maximum value that can be found in the section Crystal Oscillator Characteristics in the Electrical
Characteristics section of the product documentation.
The Reset Controller Mode Register (RSTC_MR), allowing the configuration of the Reset Controller, is powered with
VDDBU, so that its configuration is saved as long as VDDBU is on.
VDDBU, so that its configuration is saved as long as VDDBU is on.
14.4.2 NRST Manager
After power-up, NRST is an output during the ERSTL time defined in the RSTC. When ERSTL elapsed, the pin behaves
as an input and all the system is held in reset if NRST is tied to GND by an external signal.
as an input and all the system is held in reset if NRST is tied to GND by an external signal.
The NRST Manager samples the NRST input pin and drives this pin low when required by the Reset State Manager.
Figure 14-2. NRST Manager
14.4.2.1 NRST Signal
The NRST Manager handles the NRST input line asynchronously. When the line is low, a User Reset is immediately
reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the
Slow Clock to provide a safe internal de-assertion of reset.
reported to the Reset State Manager. When the NRST goes from low to high, the internal reset is synchronized with the
Slow Clock to provide a safe internal de-assertion of reset.
The level of the pin NRST can be read at any time in the bit NRSTL (NRST level) in RSTC_SR. As soon as the pin NRST
is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
is asserted, the bit URSTS in RSTC_SR is set. This bit clears only when RSTC_SR is read.
External Reset Timer
URSTS
ERSTL
exter_nreset
RSTC_MR
RSTC_SR
NRSTL
nrst_out
NRST
user_reset