Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
1108
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 46-7. SMC Timings - NCS Controlled Read and Write
Figure 46-8. SMC Timings - NRD Controlled Read and NWE Controlled Write
46.17 DDRSDRC Timings
The DDRSDRC controller satisfies the timings of standard DDR2, LP-DDR, SDR and LP-SDR modules.
DDR2, LP-DDR and SDR timings are specified by the JEDEC standard.
Supported speed grade limitations:
DDR2-400 limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK/CK#)
LP-DDR limited at 133 MHz clock frequency (1.8V, 30 pF on data/control, 10 pF on CK)
SDR-100 (3.3V, 50 pF on data/control, 10 pF on CK)
SDR-133 (3.3V, 50 pF on data/control, 10 pF on CK)
LP-SDR-133 (1.8V, 30 pF on data/control, 10 pF on CK)
NRD
NCS
D0 - D15
NWE
NCS Controlled READ
with NO HOLD
NCS Controlled READ
with HOLD
NCS Controlled WRITE
SMC22
SMC26
SMC10
SMC11
SMC12
SMC9
SMC8
SMC14
SMC14
SMC23
SMC27
SMC26
A0/A1/NBS[3:0]
/A2-A25
SMC24
SMC25
SMC12
SMC13
SMC13
NRD
NCS
D0 - D31
NWE
A0/A1/NBS[3:0]
/A2-A25
NRD Controlled READ
with NO HOLD
NWE Controlled WRITE
with NO HOLD
NRD Controlled READ
with HOLD
NWE Controlled WRITE
with HOLD
SMC1
SMC2
SMC15
SMC21
SMC3
SMC4
SMC15
SMC19
SMC20
SMC7
SMC21
SMC16
SMC7
SMC16
SMC19
SMC21
SMC17
SMC18
SMC5
SMC5
SMC6
SMC6
SMC17
SMC18