Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

Product codes
AT91SAM9X25-EK
Page of 1151
1128
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
49.
SAM9X25 Errata
49.1 External Bus Interface (EBI)
49.1.1 EBI: Data lines are Hi-Z after reset
Data lines are Hi-Z after reset. This does not affect boot capabilities neither on NOR nor on NAND memories.
Problem Fix/Workaround 
None.
49.2 Reset Controller (RSTC)
49.2.1 RSTC: Reset during SDRAM Accesses
When a Reset occurs (user reset, software reset) the SDRAM clock is turned off. Inopportunately, if this occurs at the 
same time as a SDRAM read access, the SDRAM maintains the data until the restart of the SDRAM clock.
This leads to a data bus conflict and affects adversely the boot memories connected on the EBI:
NAND Flash boot functionality, if the system boots out of the internal ROM.
NOR Flash boot, if the system boots on an external memory connected on the EBI CS0.
Problem Fix/Workaround
Two workarounds are available:
1.
Boot from Serial Flash or Data Flash on SPI.
2.
Connect the NAND Flash on D16-D23 and set NFD0_ON_D16 to 1 in the CCFG_EBICSA register.
Warning! Due to databus sharing, workaround 2 prohibits connecting another device on the EBI, even if VDDNF equals 
VDDIOM.
49.2.2 Static Memory Controller (SMC)
49.2.3 SMC: SMC DELAY I/O Registers are write-only
Contrary to what is stated in the datasheet, the SMC DELAY I/O Registers are Write-only.
Problem Fix/Workaround
None.
49.3 USB High Speed Host Port (UHPHS) and Device Port (UDPHS)
49.3.1 UHPHS/UDPHS: Bad Lock of the USB High speed transceiver DLL
The DLL used to oversample the incoming bitstream may not lock in the correct phase, leading to a bad reception of the 
incoming packets.
This issue may occur after the USB device resumes from the Suspend mode.
The DLL is used only in the High Speed mode, meaning the Full Speed mode is not impacted by this issue.
This issue may occur on the USB device after a reset leading to a SAM-BA connection issue.