Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

20

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

A first level of address decoding is performed by the AHB Bus Matrix, i.e., the implementation of the Advanced High 
performance Bus (AHB) for its Master and Slave interfaces with additional features. 

Decoding breaks up the 4 Gbytes of address space into 16 banks of 256 Mbytes. Banks 1 to 6 are directed to the EBI 
that associates these banks to the external chip selects, EBI_NCS0 to EBI_NCS5. Bank 0 is reserved for the addressing 
of the internal memories, and a second level of decoding provides 1 Mbyte of internal memory area. Bank 15 is reserved 
for the peripherals and provides access to the Advanced Peripheral Bus (APB).

Other areas are unused and performing an access within them provides an abort to the master requesting such an 
access.

The SAM9X25 embeds a total of 32 Kbytes of high-speed SRAM. 

After reset and until the Remap Command is performed, the SRAM is only accessible at address 0x0030 0000. 

After Remap, the SRAM also becomes available at address 0x0.

The SAM9X25 embeds an Internal ROM, which contains the SAM-BA

®

 program.

At any time, the ROM is mapped at address 0x0010 0000. It is also accessible at address 0x0 (BMS = 1) after the reset 
and before the Remap Command.



Integrates three External Memory Controllers:



Static Memory Controller



DDR2/SDRAM Controller



MLC NAND Flash ECC Controller



Additional logic for NAND Flash

 

and CompactFlash

®



Up to 26-bit Address Bus (up to 64 MBytes linear per chip select)



Up to 6 chip selects, Configurable Assignment:



Static Memory Controller on NCS0, NCS1, NCS2, NCS3, NCS4, NCS5



DDR2/SDRAM Controller (SDCS) or Static Memory Controller on NCS1



Optional NAND Flash support on NCS3