Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
221
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Rising edge on PIO line 7
Any edge on the other lines
The configuration required is described below.
23.5.10.2 Interrupt Mode Configuration
All the interrupt sources are enabled by writing 32’hFFFF_FFFF in PIO_IER.
Then the Additional Interrupt Mode is enabled for line 0 to 7 by writing 32’h0000_00FF in PIO_AIMER.
23.5.10.3 Edge or Level Detection Configuration
Lines 3, 4 and 5 are configured in Level detection by writing 32’h0000_0038 in PIO_LSR.
The other lines are configured in Edge detection by default, if they have not been previously configured. Otherwise, lines
0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR.
0, 1, 2, 6 and 7 must be configured in Edge detection by writing 32’h0000_00C7 in PIO_ESR.
23.5.10.4 Falling/Rising Edge or Low/High Level Detection Configuration.
Lines 0, 2, 4, 5 and 7 are configured in Rising Edge or High Level detection by writing 32’h0000_00B5 in PIO_REHLSR.
The other lines are configured in Falling Edge or Low Level detection by default, if they have not been previously
configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing
32’h0000_004A in PIO_FELLSR.
configured. Otherwise, lines 1, 3 and 6 must be configured in Falling Edge/Low Level detection by writing
32’h0000_004A in PIO_FELLSR.
Figure 23-8. Input Change Interrupt Timings if there are no Additional Interrupt Modes
23.5.11 I/O Lines Lock
When an I/O line is controlled by a peripheral (particularly the Pulse Width Modulation Controller PWM), it can become
locked by the action of this peripheral via an input of the PIO controller. When an I/O line is locked, the write of the
corresponding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which
I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to
unlock it is to apply a hardware reset to the PIO Controller.
locked by the action of this peripheral via an input of the PIO controller. When an I/O line is locked, the write of the
corresponding bit in the registers PIO_PER, PIO_PDR, PIO_MDER, PIO_MDDR, PIO_PUDR, PIO_PUER,
PIO_ABCDSR1 and PIO_ABCDSR2 is discarded in order to lock its configuration. The user can know at anytime which
I/O line is locked by reading the PIO Lock Status register PIO_LOCKSR. Once an I/O line is locked, the only way to
unlock it is to apply a hardware reset to the PIO Controller.
23.5.12 Programmable I/O Delays
The PIO interface consists of a series of signals driven by peripherals or directly by software. The simultaneous switching
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
outputs on these busses may lead to a peak of current in the internal and external power supply lines.
In order to reduce the current peak in such cases, additional propagation delays can be adjusted independently for pad
buffers by means of configuration registers, PIO_DELAY.
buffers by means of configuration registers, PIO_DELAY.
The additional programmable delays for each supporting range from 0 to 4 ns (Worst Case PVT). The delay can differ
between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal additional delay
that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
between I/Os supporting this feature. Delay can be modified per programming for each I/O. The minimal additional delay
that can be programmed on a PAD supporting this feature is 1/16 of the maximum programmable delay.
MCK
Pin Level
Read PIO_ISR
APB Access
PIO_ISR
APB Access