Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

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SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

default, last access master, fixed default master), whereas the 4-bit FIXED_DEFMSTR field selects a fixed default 
master provided that DEFMSTR_TYPE is set to fixed default master. Refer to 

After the end of the current access, if no other request is pending, the slave is disconnected from all masters.

This configuration incurs one latency clock cycle for the first access of a burst after bus Idle. Arbitration without default 
master may be used for masters that perform significant bursts or several transfers with no Idle in between, or if the slave 
bus bandwidth is widely used by one or more masters.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, 
irregardless of the number of requesting masters.

After the end of the current access, if no other request is pending, the slave remains connected to the last master that 
performed an access request.

This allows the Bus Matrix to remove the one latency cycle for the last master that accessed the slave. Other non-
privileged masters still get one latency clock cycle if they want to access the same slave. This technique is useful for 
masters that mainly perform single accesses or short bursts with some Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput 
irregardless of the number of requesting masters.

After the end of the current access, if no other request is pending, the slave connects to its fixed default master. Unlike 
the last access master, the fixed default master does not change unless the user modifies it by software 
(FIXED_DEFMSTR field of the related MATRIX_SCFG).

This allows the Bus Matrix arbiters to remove the one latency clock cycle for the fixed default master of the slave. All 
requests attempted by the fixed default master do not cause any arbitration latency, whereas other non-privileged 
masters will get one latency cycle. This technique is useful for a master that mainly performs single accesses or short 
bursts with Idle cycles in between.

This configuration provides no benefit on access latency or bandwidth when reaching maximum slave bus throughput, 
irregardless of the number of requesting masters.

The Bus Matrix provides an arbitration mechanism that reduces latency when conflict cases occur, i.e., when two or more 
masters try to access the same slave at the same time. One arbiter per AHB slave is provided, thus arbitrating each 
slave specifically.

The Bus Matrix provides the user with the possibility of choosing between two arbitration types or mixing them for each 
slave:

1.

Round-robin Arbitration (default)

2.

Fixed Priority Arbitration

The resulting algorithm may be complemented by selecting a default master configuration for each slave.

When re-arbitration is required, specific conditions apply. See