Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet

433

SAM9X25 [DATASHEET]

11054E–ATARM–10-Mar-2014

4.

An NOP command will be issued to the low-power DDR1-SDRAM. Program NOP command into the Mode Regis-
ter, the application must set Mode to 1 in the Mode Register (see 

). Perform a write 

access to any DDR1-SDRAM address to acknowledge this command. Now clocks which drive DDR1-SDRAM 
device are enabled.

A minimum pause of 200 µs will be provided to precede any signal toggle.

5.

An all banks precharge command is issued to the low-power DDR1-SDRAM. Program all banks precharge com-
mand into the Mode Register, the application must set Mode to 2 in the Mode Register (See 

). Perform a write access to any low-power DDR1-SDRAM address to acknowledge this command

6.

Two auto-refresh (CBR) cycles are provided. Program the auto refresh command (CBR) into the Mode Register, 
the application must set Mode to 4 in the Mode Register (see 

). Perform a write access 

to any low-power DDR1-SDRAM location twice to acknowledge these commands.

7.

An Extended Mode Register set (EMRS) cycle is issued to program the low-power DDR1-SDRAM parameters 
(TCSR, PASR, DS). The application must set Mode to 5 in the Mode Register (see 

) 

and perform a write access to the SDRAM to acknowledge this command.  The write address must be chosen so 
that BA[1] is set to 1 BA[0] is set to 0. For example, with a 16-bit 128 MB SDRAM (12 rows, 9 columns, 4 banks) 
bank address, the low-power DDR1-SDRAM write access should be done at address 0x20800000.

Note:

This address is for example purposes only. The real address is dependent on implementation in the product.

8.

A Mode Register set (MRS) cycle is issued to program the parameters of the low-power DDR1-SDRAM devices, in 
particular CAS latency, burst length. The application must set Mode to 3 in the Mode Register (see 

) and perform a write access to the low-power DDR1-SDRAM to acknowledge this command. The 

write address must be chosen so that BA[1:0] bits are set to 0. For example, with a 16-bit 128 MB low-power 
DDR1-SDRAM (12 rows, 9 columns, 4 banks) bank address, the SDRAM write access should be done at the 
address 0x20000000. The application must go into Normal Mode, setting Mode to 0 in the Mode Register (see 

) and performing a write access at any location in the low-power DDR1-SDRAM to 

acknowledge this command.

9.

Perform a write access to any low-power DDR1-SDRAM address.

10. Write the refresh rate into the count field in the DDRSDRC Refresh Timer register (see 

). (Refresh rate = 

delay between refresh cycles). The low-power DDR1-SDRAM device requires a refresh every 15.625 µs or 7.81 
µ

s. With a 100 MHz frequency, the refresh timer count register must to be set with (15.625*100 MHz) = 1562 i.e. 

0x061A or (7.81*100 MHz) = 781 i.e. 0x030d

11. After initialization, the low-power DDR1-SDRAM device is fully functional.

The initialization sequence is generated by software. The DDR2-SDRAM devices are initialized by the following 
sequence:

1.

Program the memory device type into the Memory Device Register (see 

). 

2.

Program the features of DDR2-SDRAM device into the Timing Register (asynchronous timing (trc, tras, etc.)), and 
into the Configuration Register (number of columns, rows, banks, cas latency and output drive strength) (see 

). 

3.

An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the appli-
cation must set Mode to 1 in the Mode Register (see 

). Perform a write access to any 

DDR2-SDRAM address to acknowledge this command. Now clocks which drive DDR2-SDRAM device are 
enabled.

A minimum pause of 200 µs is provided to precede any signal toggle.

4.

An NOP command is issued to the DDR2-SDRAM. Program the NOP command into the Mode Register, the appli-
cation must set Mode to 1 in the Mode Register (see 

). Perform a write access to any 

DDR2-SDRAM address to acknowledge this command. Now CKE is driven high.

5.

An all banks precharge command is issued to the DDR2-SDRAM. Program all banks precharge command into the 
Mode Register, the application must set Mode to 2 in the Mode Register (See 

form a write access to any DDR2-SDRAM address to acknowledge this command