Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
440
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 30-10.SINGLE Write Access Followed By A Read Access, DDR2 -SDRAM Device
30.5.2 SDRAM Controller Read Cycle
The DDRSDRC allows burst access or single access in normal mode (mode =000). Whatever access type, the
DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
DDRSDRC keeps track of the active row in each bank, thus maximizing performance of the DDRSDRC.
The SDRAM devices are programmed with a burst length equal to 8 which determines the length of a sequential data
output by the read command that is set to 8. The latency from read command to data output is equal to 2 or 3. This value
is programmed during the initialization phase (see
output by the read command that is set to 8. The latency from read command to data output is equal to 2 or 3. This value
is programmed during the initialization phase (see
).
To initiate a single access, the DDRSDRC checks if the page access is already open. If row/bank addresses match with
the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if
bank addresses are identical but the row addresses are not identical, the controller generates a precharge command,
activates the new row and initiates a read command. To comply with SDRAM timing parameters, additional clock cycles
are inserted between precharge/active (Trp) commands and active/read (Trcd) command. After a read command,
additional wait states are generated to comply with cas latency. The DDRSDRC supports a cas latency of two, two and
half, and three (2 or 3 clocks delay). As the burst length is fixed to 8, in the case of single access or burst access inferior
to 8 data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop Command (BST) is
used to stop output during a burst read.
the previous row/bank addresses, the controller generates a read command. If the bank addresses are not identical or if
bank addresses are identical but the row addresses are not identical, the controller generates a precharge command,
activates the new row and initiates a read command. To comply with SDRAM timing parameters, additional clock cycles
are inserted between precharge/active (Trp) commands and active/read (Trcd) command. After a read command,
additional wait states are generated to comply with cas latency. The DDRSDRC supports a cas latency of two, two and
half, and three (2 or 3 clocks delay). As the burst length is fixed to 8, in the case of single access or burst access inferior
to 8 data requests, it has to stop the burst otherwise seven or X values could be read. Burst Stop Command (BST) is
used to stop output during a burst read.
To initiate a burst access, the DDRSDRC checks the transfer type signal. If the next accesses are sequential read
accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an
automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is generated.
accesses, reading to the SDRAM device is carried out. If the next access is a read non-sequential access, then an
automatic page break can be inserted. If the bank addresses are not identical or if bank addresses are identical but the
row addresses are not identical, the controller generates a precharge command, activates the new row and initiates a
read command. In the case where the page access is already open, a read command is generated.
To comply with SDRAM timing parameters, additional clock cycles are inserted between precharge/active (Trp)
commands and active/read (Trcd) commands. The DDRSDRC supports a cas latency of two, two and half, and three (2
or 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the
performance of the controller. Depending on the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. In the
case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the
next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the DDRSDRC
anticipates 2 or 3 read accesses.
commands and active/read (Trcd) commands. The DDRSDRC supports a cas latency of two, two and half, and three (2
or 3 clocks delay). During this delay, the controller uses internal signals to anticipate the next access and improve the
performance of the controller. Depending on the latency(2/3), the DDRSDRC anticipates 2 or 3 read accesses. In the
case of burst of specified length, accesses are not anticipated, but if the burst is broken (border, busy mode, etc.), the
next access is treated as an incrementing burst of unspecified length, and in function of the latency(2/3), the DDRSDRC
anticipates 2 or 3 read accesses.
For a definition of timing parameters, refer to
.
Row a
col a
NOP PRCHG NOP
ACT
NOP
WRITE
NOP
READ
NOP
0
Data masked
SDCLK
A[12:0]
COMMAND
BA[1:0]
DQS[1:0]
Da Db
Da
Db
D[15:0]
3
0
3
DM[1:0]
twtr