Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
475
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
31.2.2 DMA Controller 1
Two Masters
Embeds 8 channels
16-byte FIFO per Channel
Features:
Linked List support with Status Write Back operation at End of Transfer
Word, HalfWord, Byte transfer support.
Peripheral to memory
Memory to peripheral
The DMA controller can handle the transfer between peripherals and memory and so receives the triggers from the
peripherals below. The hardware interface numbers are also given in
peripherals below. The hardware interface numbers are also given in
Table 31-2. DMA Channel Definition
Instance name
T/R
DMA Channel HW
Interface Number
HSMCI1
RX/TX
0
SPI1
TX
1
SPI1
RX
2
SMD
TX
3
SMD
RX
4
TWI1
TX
5
TWI1
RX
6
ADC
RX
7
DBGU
TX
8
DBGU
RX
9
UART1
TX
10
UART1
RX
11
USART2
TX
12
USART2
RX
13
USART3
TX
14
USART3
RX
15