Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
622
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
–FC field is programmed with peripheral to memory flow control mode.
–Both SRC_DSCR and DST_DSCR are set to 1 (descriptor fetch is disabled) or Next descriptor
location points to 0.
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, DMA Controller is able
to prefetch data and write HSMCI simultaneously.
15. Program LLI_B.DMAC_CFGx memory location for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.
–SRC_H2SEL is set to true to enable hardware handshaking on the destination.
–SRC_PER is programmed with the hardware handshaking ID of the targeted HSMCI Host
Controller.
16. Program LLI_B.DMAC_DSCR with 0.
17. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI fetch
17. Program the DMAC_CTRLBx register for Channel x with 0. its content is updated with the LLI fetch
operation.
18. Program DMAC_DSCRx with the address of LLI_W if block_length greater than 4 else with address of
LLI_B.
19. Enable Channel x writing one to DMAC_CHER[x]. The DMAC is ready and waiting for request.
3.
Wait for XFRDONE in the HSMCI_SR register.
34.8.6.3 Block Length is Not Multiple of 4, with Padding Value (ROPT field in HSMCI_DMA register set to 1)
When the ROPT field is set to one, The DMA Controller performs only WORD access on the bus to transfer a non-
multiple of 4 block length. Unlike previous flow, in which the transfer size is rounded to the nearest multiple of 4.
multiple of 4 block length. Unlike previous flow, in which the transfer size is rounded to the nearest multiple of 4.
1.
Program the HSMCI Interface, see previous flow.
ROPT field is set to 1.
2.
Program the DMA Controller
1. Read the channel register to choose an available (disabled) channel.
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
2. Clear any pending interrupts on the channel from the previous DMA transfer by reading the DMAC_EBCISR
register.
3. Program the channel registers.
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO
4. The DMAC_SADDRx register for Channel x must be set with the starting address of the HSMCI_FIFO
address.
5. The DMAC_DADDRx register for Channel x must be word aligned.
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
6. Program the DMAC_CTRLAx register of Channel x with the following field’s values:
–DST_WIDTH is set to WORD
–SRC_WIDTH is set to WORD
–SCSIZE must be set according to the value of HSMCI_DMA.CHKSIZE Field.
–BTSIZE is programmed with CEILING(block_length/4).
7. Program the DMAC_CTRLBx register for Channel x with the following field’s values:
–DST_INCR is set to INCR
–SRC_INCR is set to INCR
–FC field is programmed with peripheral to memory flow control mode.
–both DST_DSCR and SRC_DSCR are set to 1. (descriptor fetch is disabled)
–DIF and SIF are set with their respective layer ID. If SIF is different from DIF, the DMA Controller is
able to prefetch data and write HSMCI simultaneously.
8. Program the DMAC_CFGx register for Channel x with the following field’s values:
–FIFOCFG defines the watermark of the DMA channel FIFO.