Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
669
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
Figure 35-8. Programmable Delays
35.7.3.5 Peripheral Selection
The serial peripherals are selected through the assertion of the NPCS0 to NPCS3 signals. By default, all the NPCS
signals are high before and after each transfer.
signals are high before and after each transfer.
Fixed Peripheral Select: SPI exchanges data with only one peripheral
Fixed Peripheral Select is activated by writing the PS bit to zero in SPI_MR (Mode Register). In this case, the current
peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
peripheral is defined by the PCS field in SPI_MR and the PCS field in the SPI_TDR has no effect.
Variable Peripheral Select: Data can be exchanged with more than one peripheral without having to reprogram the
NPCS field in the SPI_MR register.
NPCS field in the SPI_MR register.
Variable Peripheral Select is activated by setting PS bit to one. The PCS field in SPI_TDR is used to select the current
peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR
register as the following format.
peripheral. This means that the peripheral selection can be defined for each new data. The value to write in the SPI_TDR
register as the following format.
[xxxxxxx(7-bit) + LASTXFER(1-bit)
+ xxxx(4-bit) + PCS (4-bit) + DATA (8 to 16-bit)] with PCS equals to the chip select
to assert as defined in
(SPI Transmit Data Register) and LASTXFER bit at 0 or 1 depending on CSAAT
bit.
Note:
Note:
1. Optional.
CSAAT, LASTXFER bits are discussed in
If LASTXFER is used, the command must be issued before writing the last character. Instead of LASTXFER, the user
can use the SPIDIS command. After the end of the DMA transfer, wait for the TXEMPTY flag, then write SPIDIS into the
SPI_CR register (this will not change the configuration register values); the NPCS will be deactivated after the last
character transfer. Then, another DMA transfer can be started if the SPIEN was previously written in the SPI_CR
register.
can use the SPIDIS command. After the end of the DMA transfer, wait for the TXEMPTY flag, then write SPIDIS into the
SPI_CR register (this will not change the configuration register values); the NPCS will be deactivated after the last
character transfer. Then, another DMA transfer can be started if the SPIEN was previously written in the SPI_CR
register.
35.7.3.6 SPI Direct Access Memory Controller (DMAC)
In both fixed and variable mode the Direct Memory Access Controller (DMAC) can be used to reduce processor
overhead.
overhead.
The Fixed Peripheral Selection allows buffer transfers with a single peripheral. Using the DMAC is an optimal means, as
the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral
selection requires the Mode Register to be reprogrammed.
the size of the data transfer between the memory and the SPI is either 8 bits or 16 bits. However, changing the peripheral
selection requires the Mode Register to be reprogrammed.
The Variable Peripheral Selection allows buffer transfers with multiple peripherals without reprogramming the Mode
Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is
destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and
LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the
buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the
processor.
Register. Data written in SPI_TDR is 32 bits wide and defines the real data to be transmitted and the peripheral it is
destined to. Using the DMAC in this mode requires 32-bit wide buffers, with the data in the LSBs and the PCS and
LASTXFER fields in the MSBs, however the SPI still controls the number of bits (8 to16) to be transferred through MISO
and MOSI lines with the chip select configuration registers. This is not the optimal means in term of memory size for the
buffers, but it provides a very effective means to exchange data with several peripherals without any intervention of the
processor.
DLYBCS
DLYBS
DLYBCT
DLYBCT
Chip Select 1
Chip Select 2
SPCK