Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
796
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
39.7.1 Baud Rate Generator
The Baud Rate Generator provides the bit period clock named the Baud Rate Clock to both the receiver and the
transmitter.
transmitter.
The Baud Rate Generator clock source can be selected by setting the USCLKS field in the Mode Register (US_MR)
between:
between:
The Master Clock MCK
A division of the Master Clock, the divider being product dependent, but generally set to 8
The external clock, available on the SCK pin
The Baud Rate Generator is based upon a 16-bit divider, which is programmed with the CD field of the Baud Rate
Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD
is programmed to 1, the divider is bypassed and becomes inactive.
Generator Register (US_BRGR). If CD is programmed to 0, the Baud Rate Generator does not generate any clock. If CD
is programmed to 1, the divider is bypassed and becomes inactive.
If the external SCK clock is selected, the duration of the low and high levels of the signal provided on the SCK pin must
be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times
lower than MCK in USART mode, or 6 times lower in SPI mode.
be longer than a Master Clock (MCK) period. The frequency of the signal provided on SCK must be at least 4.5 times
lower than MCK in USART mode, or 6 times lower in SPI mode.
Figure 39-3. Baud Rate Generator
39.7.1.1 Baud Rate in Asynchronous Mode
If the USART is programmed to operate in asynchronous mode, the selected clock is first divided by CD, which is field
programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a
sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
programmed in the Baud Rate Generator Register (US_BRGR). The resulting clock is provided to the receiver as a
sampling clock and then divided by 16 or 8, depending on the programming of the OVER bit in US_MR.
If OVER is set to 1, the receiver sampling is 8 times higher than the baud rate clock. If OVER is cleared, the sampling is
performed at 16 times the baud rate clock.
performed at 16 times the baud rate clock.
The following formula performs the calculation of the Baud Rate.
This gives a maximum baud rate of MCK divided by 8, assuming that MCK is the highest possible clock and that OVER
is programmed to 1.
is programmed to 1.
Baud Rate Calculation Example
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Baudrate
SelectedClock
8 2 Over
–
(
)CD
(
)
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