Atmel Evaluation Kit AT91SAM9X25-EK AT91SAM9X25-EK Data Sheet
Product codes
AT91SAM9X25-EK
960
SAM9X25 [DATASHEET]
11054E–ATARM–10-Mar-2014
For example, if channel 4 is disabled (ADC_CSR[4] = 0), ADC_SEQR1, ADC_SEQR2 register bitfields USCH1 up to
USCH12 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior.
USCH12 must not contain the value 4. Thus the length of the user sequence may be limited by this behavior.
As an example, if only 4 channels over 12 (CH0 up to CH3) are selected for ADC conversions, the user sequence length
cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any combination of
channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible).
cannot exceed 4 channels. Each trigger event may launch up to 4 successive conversions of any combination of
channels 0 up to 3 but no more (i.e. in this case the sequence CH0, CH0, CH1, CH1, CH1 is impossible).
A sequence that repeats several times the same channel requires more enabled channels than channels actually used
for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled channels (4 free channels on
application boards) whereas only CH0, CH1 are really converted.
Note:
for conversion. For example, a sequence like CH0, CH0, CH1, CH1 requires 4 enabled channels (4 free channels on
application boards) whereas only CH0, CH1 are really converted.
Note:
The reference voltage pins always remain connected in normal mode as in sleep mode.
42.6.7 Comparison Window
The ADC Controller features automatic comparison functions. It compares converted values to a low threshold or a high
threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The
comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all
channels the CMP_ALL parameter of ADC_EMR should be set.
threshold or both, according to the CMPMODE function chosen in the Extended Mode Register (ADC_EMR). The
comparison can be done on all channels or only on the channel specified in CMPSEL field of ADC_EMR. To compare all
channels the CMP_ALL parameter of ADC_EMR should be set.
Moreover a filtering option can be set by writing the number of consecutive comparison errors needed to raise the flag.
This number can be written and read in the CMPFILTER field of ADC_EMR.
This number can be written and read in the CMPFILTER field of ADC_EMR.
The flag can be read on the COMPE bit of the Interrupt Status Register (ADC_ISR) and can trigger an interrupt.
The High Threshold and the Low Threshold can be read/write in the Comparison Window Register (ADC_CWR).
If the comparison window is to be used with LOWRES bit in ADC_MR set to 1, the thresholds do not need to be adjusted
as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in
consideration of the maximum ADC resolution.
as adjustment will be done internally. Whether or not the LOWRES bit is set, thresholds must always be configured in
consideration of the maximum ADC resolution.
42.6.8 ADC Timings
Each ADC has its own minimal Startup Time that is programmed through the field STARTUP in the Mode Register,
ADC_MR.
ADC_MR.
A minimal Tracking Time is necessary for the ADC to guarantee the best converted final value between two channel
selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
selections. This time has to be programmed through the TRACKTIM bit field in the Mode Register, ADC_MR.
Warning: No input buffer amplifier to isolate the source is included in the ADC. This must be taken into consideration to
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
program a precise value in the TRACKTIM field. See the product ADC Characteristics section.
42.6.9 Buffer Structure
The DMA read channel is triggered each time a new data is stored in ADC_LCDR register. The same structure of data is
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data transferred to DMA buffer, carried
on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4
most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better
checking the DMA buffer integrity.
repeatedly stored in ADC_LCDR register each time a trigger event occurs. Depending on user mode of operation
(ADC_MR, ADC_CHSR, ADC_SEQR1, ADC_SEQR2) the structure differs. Each data transferred to DMA buffer, carried
on a half-word (16-bit), consists of last converted data right aligned and when TAG is set in ADC_EMR register, the 4
most significant bits are carrying the channel number thus allowing an easier post-processing in the DMA buffer or better
checking the DMA buffer integrity.