Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 Data Sheet

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SAM4S [DATASHEET]

11100E–ATARM–24-Jul-13

default master provided that DEFMSTR_TYPE is set to fixed default master. Please refer to the Bus Matrix user interface
description.

The Bus Matrix provides an arbitration mechanism that allows to reduce latency when conflict cases occur, basically
when two or more masters try to access the same slave at the same time. One arbiter per AHB slave is provided,
allowing to arbitrate each slave differently.

The Bus Matrix provides to the user the possibility to choose between 2 arbitration types, and this for each slave:

1.

Round-Robin Arbitration (the default)

2.

Fixed Priority Arbitration

This choice is given through the field ARBT of the Slave Configuration Registers (MATRIX_SCFG).

Each algorithm may be complemented by selecting a default master configuration for each slave.

When a re-arbitration has to be done, it is realized only under some specific conditions detailed in the following
paragraph.

Each arbiter has the ability to arbitrate between two or more different master’s requests. In order to avoid burst breaking
and also to provide the maximum throughput for slave interfaces, arbitration may only take place during the following
cycles:

1.

Idle Cycles: when a slave is not connected to any master or is connected to a master which is not currently 
accessing it.

2.

Single Cycles: when a slave is currently doing a single access.

3.

End of Burst Cycles: when the current cycle is the last cycle of a burst transfer. For defined length burst, predicted 
end of burst matches the size of the transfer but is managed differently for undefined length burst (See 

4.

Slot Cycle Limit: when the slot cycle counter has reached the limit value indicating that the current master access 
is too long and must be broken (See 

In order to avoid too long slave handling during undefined length bursts (INCR), the Bus Matrix provides specific logic in
order to re-arbitrate before the end of the INCR transfer.

A predicted end of burst is used for defined length burst transfer, which is selected between the following:

1.

Infinite: no predicted end of burst is generated and therefore INCR burst transfer will never be broken.

2.

 Four beat bursts: predicted end of burst is generated at the end of each four beat boundary inside INCR transfer.

3.

Eight beat bursts: predicted end of burst is generated at the end of each eight beat boundary inside INCR transfer.

4.

Sixteen beat bursts: predicted end of burst is generated at the end of each sixteen beat boundary inside INCR 
transfer.

This selection can be done through the field ULBT of the Master Configuration Registers (MATRIX_MCFG).

The Bus Matrix contains specific logic to break too long accesses such as very long bursts on a very slow slave (e.g. an
external low speed memory). At the beginning of the burst access, a counter is loaded with the value previously written in
the SLOT_CYCLE field of the related Slave Configuration Register (MATRIX_SCFG) and decreased at each clock cycle.
When the counter reaches zero, the arbiter has the ability to re-arbitrate at the end of the current byte, half word or word
transfer.

This algorithm allows the Bus Matrix arbiters to dispatch the requests from different masters to the same slave in a
round-robin manner. If two or more master’s requests arise at the same time, the master with the lowest number is first
serviced then the others are serviced in a round-robin manner.