Atmel SAM4S-EK2 Atmel ATSAM4S-EK2 ATSAM4S-EK2 Data Sheet
Product codes
ATSAM4S-EK2
403
SAM4S [DATASHEET]
11100E–ATARM–24-Jul-13
If a null hold value is programmed on NWE, the SMC can guarantee a positive hold of address and NCS signal after the
rising edge of NWE. This is true for WRITE_MODE = 1 only. See
rising edge of NWE. This is true for WRITE_MODE = 1 only. See
For read and write operations: a null value for pulse parameters is forbidden and may lead to unpredictable behavior.
In read and write cycles, the setup and hold time parameters are defined in reference to the address bus. For external
devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals
(write), these setup and hold times must be converted into setup and hold times in reference to the address bus.
devices that require setup and hold time between NCS and NRD signals (read), or between NCS and NWE signals
(write), these setup and hold times must be converted into setup and hold times in reference to the address bus.
26.9
Scrambling/Unscrambling Function
The external data bus D[7:0] can be scrambled in order to prevent intellectual property data located in off-chip memories
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
from being easily recovered by analyzing data at the package pin level of either microcontroller or memory device.
The scrambling and unscrambling are performed on-the-fly without additional wait states.
The scrambling method depends on two user-configurable key registers, SMC_KEY1 and SMC_KEY2. These key
registers are only accessible in write mode.
registers are only accessible in write mode.
The key must be securely stored in a reliable non-volatile memory in order to recover data from the off-chip memory. Any
data scrambled with a given key cannot be recovered if the key is lost.
data scrambled with a given key cannot be recovered if the key is lost.
The scrambling/unscrambling function can be enabled or disabled by programming the SMC_OCMS register.
When multiple chip selects are handled, it is possible to configure the scrambling function per chip select using the
OCMS field in the SMC_OCMS registers.
OCMS field in the SMC_OCMS registers.
26.10 Automatic Wait States
Under certain circumstances, the SMC automatically inserts idle cycles between accesses to avoid bus contention or
operation conflict.
operation conflict.
26.10.1 Chip Select Wait States
The SMC always inserts an idle cycle between 2 transfers on separate chip selects. This idle cycle ensures that there is
no bus contention between the de-activation of one device and the activation of the next one.
no bus contention between the de-activation of one device and the activation of the next one.
During chip select wait state, all control lines are turned inactive: NWR, NCS[0..3], NRD lines are all set to 1.