Atmel SAM4L Xplained Pro Starter Kit Atmel ATSAM4L-XSTK ATSAM4L-XSTK Data Sheet

Product codes
ATSAM4L-XSTK
Page of 173
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42023ES–SAM–07/2013
ATSAM4L8/L4/L2
At power-up or after a reset, the ATSAM4L8/L4/L2 is in the RUN0 mode. Only the necessary
clocks are enabled allowing software execution. The Power Manager (PM) can be used to adjust
the clock frequencies and to enable and disable the peripheral clocks.
When the CPU is entering a Power Save Mode, the CPU stops executing code. The user can
choose between four Power Save Modes to optimize power consumption:
• SLEEP mode: the Cortex-M4 core is stopped, optionally some clocks are stopped, 
peripherals are kept running if enabled by the user.
• WAIT mode: all clock sources are stopped, the core and all the peripherals are stopped 
except the modules running with the 32kHz clock if enabled. This is the lowest power 
configuration where SleepWalking is supported.
• RETENTION mode: similar to the WAIT mode in terms of clock activity. This is the lowest 
power configuration where the logic is retained.
• BACKUP mode: the Core domain is powered off, the Backup domain is kept powered.
A wake up source exits the system to the RUN mode from which the Power Save Mode was
entered.
A reset source always exits the system from the Power Save Mode to the RUN0 mode.
The configuration of the I/O lines are maintained in all Power Save Modes. Refer to 
7.1.1
SLEEP mode
The SLEEP mode allows power optimization with the fastest wake up time.
The CPU is stopped. To further reduce power consumption, the user can switch off modules-
clocks and synchronous clock sources through the BPM.PMCON.SLEEP field (See 
).
The required modules will be halted regardless of the bit settings of the mask registers in the
Power Manager (PM.AHBMASK, PM.APBxMASK).
Notes:
1. from modules with clock running.
2. OSC32K and RC32K will only remain operational if pre-enabled.
7.1.1.1
Entering SLEEP mode
The SLEEP mode is entered by executing the WFI instruction.
 
Additionally, if the SLEEPONEXIT bit in the Cortex-M4 System Control Register (SCR) is set,
the SLEEP mode will also be entered when the Cortex-M4 exits the lowest priority ISR. This
Table 7-1.
SLEEP mode Configuration
BPM.PSAVE.SLEEP
CPU 
clock
AHB 
clocks
APB clocks
GCLK
Clock sources: 
OSC, RCFAST, 
RC80M, PLL, 
DFLL
RCSYS
OSC32K
RC32K
Wake up Sources
0
Stop
Run
Run
Run
Run
Run
Any interrupt
1
Stop
Stop
Run
Run
Run
Run
Any interrupt
2
Stop
Stop
Stop
Run
Run
Run
Any interrupt
3
Stop
Stop
Stop
Stop
Run
Run
Any interrupt