Atmel ARM-Based Evaluation Kit for SAM4S16C, 32-Bit ARM® Cortex® Microcontroller ATSAM4S-WPIR-RD ATSAM4S-WPIR-RD Data Sheet
Product codes
ATSAM4S-WPIR-RD
13
SAM4S-WPIR-RD [USER GUIDE]
42060A–ATARM–12/2012
Figure 4-9.
Backlight Control
LED_A
LED_K4
LED_K3
LED_K2
LED_K1
C64
1uF
1uF
C66
1uF
1uF
C65
1uF
1uF
R58
47K
47K
C67
4.7uF
4.7uF
B2
BN03K314S300R
BN03K314S300R
R59
0R
0R
MN10
AAT3155ITP
C1+
10
C1-
9
EN/SET
11
C2+
7
C2-
6
OUTCP
8
IN
5
GND
4
D1
3
D2
2
D3
1
D4
12
+3V_LCD
+3V_LCD
DGND
DGND
PC13
4.3
Connectors
4.3.1
JTAG/ICE Connector
Figure 4-10.
JTAG J2
Table 4-3. JTAG/ICE Connector J2 Signal Descriptions
Pin
Mnemonic
Description
1
VTref. 3.3V power
This is the target reference voltage. It is used to check if the target has power,
to create the logic-level reference for the input comparators, and to control the
output logic levels to the target. It is normally fed from VDD on the target board
and must not have a series resistor.
to create the logic-level reference for the input comparators, and to control the
output logic levels to the target. It is normally fed from VDD on the target board
and must not have a series resistor.
2
Vsupply. 3.3V power
This pin is not connected in SAM-ICE. It is reserved for compatibility with other
equipment. Connect to VDD or leave open in target system.
equipment. Connect to VDD or leave open in target system.
3
nTRST TARGET RESET - Active-low output
signal that resets the target
JTAG Reset. Output from SAM-ICE to the Reset signal on the target JTAG port.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
Typically connected to nTRST on the target CPU. This pin is normally pulled
HIGH on the target to avoid unintentional resets when there is no connection.
4
GND
Common ground
5
TDI TEST DATA INPUT - Serial data output
line, sampled on the rising edge of the TCK
signal.
line, sampled on the rising edge of the TCK
signal.
JTAG data input of target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TDI on target CPU.
defined state on the target board. Typically connected to TDI on target CPU.
6
GND
Common ground
7
TMS TEST MODE SELECT
JTAG mode set input of target CPU. This pin should be pulled up on the target.
Typically connected to TMS on target CPU. Output signal that sequences the
target's JTAG state machine, sampled on the rising edge of the TCK signal.
Typically connected to TMS on target CPU. Output signal that sequences the
target's JTAG state machine, sampled on the rising edge of the TCK signal.
8
GND
Common ground
9
TCK TEST CLOCK - Output timing signal,
for synchronizing test logic and control
register access.
for synchronizing test logic and control
register access.
JTAG clock signal to target CPU. It is recommended that this pin is pulled to a
defined state on the target board. Typically connected to TCK on target CPU.
defined state on the target board. Typically connected to TCK on target CPU.