Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

1015

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

ISI_SR

0xF8048028

Read-only

Reset:  

0x00000000

0: Module is disabled.

1: Module is enabled.

1: Disable request has completed. This flag is reset after a read operation.

1: Software reset request has completed. This flag is reset after a read operation.

0: Indicates that no Codec request is pending.

1: Indicates that the request has been taken into account but cannot be serviced within the current frame. The operation is post-
poned to the next frame.

1: Indicates that a Vertical synchronization has been detected since the last read of the status register.

When set to one, this bit indicates that the DATA transfer on the preview channel has completed. This flag is reset after a read 
operation.

When set to one, this bit indicates that the DATA transfer on the codec channel has completed. This flag is reset after a read 
operation.

When the status of the preview or codec DMA channel is modified, a minimum amount of time is required to perform the clock 
domain synchronization. This bit is set when this operation occurs. No modification of the channel status is allowed when this bit 
is set, to guarantee data integrity.

31

30

29

28

27

26

25

24

–

–

–

–

FR_OVR

CRC_ERR

C_OVR

P_OVR

23

22

21

20

19

18

17

16

–

–

–

–

SIP

–

CXFR_DONE

PXFR_DONE

15

14

13

12

11

10

9

8

–

–

–

–

–

VSYNC

–

CDC_PND

7

6

5

4

3

2

1

0

–

–

–

–

–

SRST

DIS_DONE

ENABLE