Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1040
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
group/individual bit: this is One for multicast addresses and Zero for unicast. The All Ones address is the broadcast
address, and a special case of multicast.
address, and a special case of multicast.
The EMAC supports recognition of four specific addresses. Each specific address requires two registers, specific
address register bottom and specific address register top. Specific address register bottom stores the first four bytes of
the destination address and specific address register top contains the last two bytes. The addresses stored can be
specific, group, local or universal.
address register bottom and specific address register top. Specific address register bottom stores the first four bytes of
the destination address and specific address register top contains the last two bytes. The addresses stored can be
specific, group, local or universal.
The destination address of received frames is compared against the data stored in the specific address registers once
they have been activated. The addresses are deactivated at reset or when their corresponding specific address register
bottom is written. They are activated when specific address register top is written. If a receive frame address matches an
active address, the frame is copied to memory.
they have been activated. The addresses are deactivated at reset or when their corresponding specific address register
bottom is written. They are activated when specific address register top is written. If a receive frame address matches an
active address, the frame is copied to memory.
The following example illustrates the use of the address match registers for a MAC address of 21:43:65:87:A9:CB.
Preamble 55
SFD D5
DA (Octet0 - LSB) 21
DA(Octet 1) 43
DA(Octet 2) 65
DA(Octet 3) 87
DA(Octet 4) A9
DA (Octet5 - MSB) CB
SA (LSB) 00
SA 00
SA 00
SA 00
SA 00
SA (MSB) 43
SA (LSB) 21
The sequence above shows the beginning of an Ethernet frame. Byte order of transmission is from top to bottom as
shown. For a successful match to specific address 1, the following address matching registers must be set up:
shown. For a successful match to specific address 1, the following address matching registers must be set up:
Base address + 0x98 0x87654321 (Bottom)
Base address + 0x9C 0x0000CBA9 (Top)
And for a successful match to the Type ID register, the following should be set up:
Base address + 0xB8 0x00004321
45.4.7 Broadcast Address
The broadcast address of 0xFFFFFFFFFFFF is recognized if the ‘no broadcast’ bit in the network configuration register is
zero.
zero.