Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

Product codes
AT91SAM9G25-EK
Page of 1165
1045
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
45.5.1.7  Receiving Frames
When a frame is received and the receive circuits are enabled, the EMAC checks the address and, in the following 
cases, the frame is written to system memory:
If it matches one of the four specific address registers.
If it matches the hash address function.
If it is a broadcast address (0xFFFFFFFFFFFF) and broadcasts are allowed.
If the EMAC is configured to copy all frames.
The register receive buffer queue pointer points to the next entry (see 
) and the EMAC uses this 
as the address in system memory to write the frame to. Once the frame has been completely and successfully received 
and written to system memory, the EMAC then updates the receive buffer descriptor entry with the reason for the 
address match and marks the area as being owned by software. Once this is complete an interrupt receive complete is 
set. Software is then responsible for handling the data in the buffer and then releasing the buffer by writing the ownership 
bit back to 0.
If the EMAC is unable to write the data at a rate to match the incoming frame, then an interrupt receive overrun is set. If 
there is no receive buffer available, i.e., the next buffer is still owned by software, the interrupt receive buffer not available 
is set. If the frame is not successfully received, a statistic register is incremented and the frame is discarded without 
informing software.