Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1118
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
46.18 Peripheral Timings
46.18.1 SPI
46.18.1.1 Maximum SPI Frequency
The following formulas give maximum SPI frequency in Master read and write modes and in Slave read and write modes.
Master Write Mode
The SPI is only sending data to a slave device such as an LCD, for example. The limit is given by SPI
2
(or SPI
5
)
timing. Since it gives a maximum frequency above the maximum pad speed (see
), the maxi-
mum SPI frequency is the one from the pad.
Master Read Mode
t
valid
is the slave time response to output data after deleting an SPCK edge. For Atmel SPI DataFlash
(AT45DB642D), t
valid
(or t
v
) is 12 ns Max.
This gives f
SPCK
Max = 39 MHz @ V
DDIO
= 3.3V.
Slave Read Mode
In slave mode, SPCK is the input clock for the SPI. The max SPCK frequency is given by setup and hold timings
SPI
SPI
7
/SPI
8
(or SPI
10
/SPI
11
). Since this gives a frequency well above the pad limit, the limit in slave read mode is
given by SPCK pad.
Slave Write Mode
t
setup
is the setup time from the master before sampling data (12 ns).
This gives f
SPCK
Max = 39 MHz @ V
DDIO
= 3.3V.
46.18.1.2 Timing Conditions
Timings are given assuming a capacitance load on
MISO, SPCK and MOSI.
46.18.1.3 Timing Extraction
Figure 46-9. SPI Master mode 1 and 2
f
SPCK
Max
1
SPI
0
or SPI
3
(
)
t
valid
+
----------------------------------------------------------
=
f
SPCK
Max
1
SPI
6
or SPI
9
(
)
t
setup
+
------------------------------------------------------------
=
Table 46-36. Capacitance Load for MISO, SPCK and MOSI (product dependent)
Supply
Corner
Max
Min
3.3V
40 pF
5 pF
1.8V
20 pF
5 pF
SPCK
MISO
MOSI
SPI
2
SPI
0
SPI
1