Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
1126
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 46-23.Minimum and Maximum Access Time of Output Signals
46.18.3 ISI
46.18.3.1 Timing conditions
Timings are given assuming capacitance loads as defined in
46.18.3.2 Timing Extraction
Figure 46-24.ISI Timing Diagram
TK (CKI =0)
TF/TD
SSC
0min
TK (CKI =1)
SSC
0max
Table 46-41. Capacitance Load
Supply
Corner
Max
Typical Voltage High
Temperature
Min
3.3V
30 pF
30 pF
0 pF
1.8V
20 pF
20 pF
0 pF
PIXCLK
DATA[7:0]
VSYNC
HSYNC
VSYNC
HSYNC
Valid Data
Valid Data
Valid Data
1
2
3
Table 46-42. ISI Timings with Peripheral Supply 3.3V
Symbol
Parameter
Min
Max
Unit
ISI
1
DATA/VSYNC/HSYNC setup time
t
PIXCLK
/2 + 0.3
ns
ISI
2
DATA/VSYNC/HSYNC hold time
-t
PIXCLK
/2 - 3.4
ns
ISI
3
PIXCLK frequency
54 MHz
MHz
Table 46-43. ISI Timings with Peripheral Supply 1.8V
Symbol
Parameter
Min
Max
Unit
ISI
1
DATA/VSYNC/HSYNC setup time
t
PIXCLK
/2 + 0.5
ns
ISI
2
DATA/VSYNC/HSYNC hold time
-t
PIXCLK
/2 - 3.6
ns
ISI
3
PIXCLK frequency
54 MHz
MHz