Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

Product codes
AT91SAM9G25-EK
Page of 1165
208
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
22.13.13 PMC SMD Clock Register
Name:
PMC_SMD
Address:
0xFFFFFC3C
Access :
Read-write 
• SMDS: SMD input clock selection
0 = SMD Clock Input is PLLA
1 = SMD Clock Input is UPLL
• SMDDIV: Divider for SMD Clock.
SMD Clock is Input clock divided by SMD +1
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
SMDDIV
7
6
5
4
3
2
1
0
SMDS