Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
290
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 24-5. Character Reception
24.5.2.3 Receiver Ready
When a complete character is received, it is transferred to the DBGU_RHR and the RXRDY status bit in DBGU_SR
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
(Status Register) is set. The bit RXRDY is automatically cleared when the receive holding register DBGU_RHR is read.
Figure 24-6. Receiver Ready
24.5.2.4 Receiver Overrun
If DBGU_RHR has not been read by the software (or the Peripheral Data Controller or DMA Controller) since the last
transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is
cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
transfer, the RXRDY bit is still set and a new character is received, the OVRE status bit in DBGU_SR is set. OVRE is
cleared when the software writes the control register DBGU_CR with the bit RSTSTA (Reset Status) at 1.
Figure 24-7. Receiver Overrun
24.5.2.5 Parity Error
Each time a character is received, the receiver calculates the parity of the received data bits, in accordance with the field
PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
PAR in DBGU_MR. It then compares the result with the received parity bit. If different, the parity error bit PARE in
DBGU_SR is set at the same time the RXRDY is set. The parity bit is cleared when the control register DBGU_CR is
written with the bit RSTSTA (Reset Status) at 1. If a new character is received before the reset status command is
written, the PARE bit remains at 1.
Figure 24-8. Parity Error
D0
D1
D2
D3
D4
D5
D6
D7
DRXD
True Start Detection
Sampling
Parity Bit
Stop Bit
Example: 8-bit, parity enabled 1 stop
1 bit
period
0.5 bit
period
period
D0
D1
D2
D3
D4
D5
D6
D7
P
S
S
D0
D1
D2
D3
D4
D5
D6
D7
P
DRXD
Read DBGU_RHR
RXRDY
D0
D1
D2
D3
D4
D5
D6
D7
P
S
S
D0
D1
D2
D3
D4
D5
D6
D7
P
DRXD
RSTSTA
RXRDY
OVRE
stop
stop
stop
D0
D1
D2
D3
D4
D5
D6
D7
P
S
DRXD
RSTSTA
RXRDY
PARE
Wrong Parity Bit