Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

Product codes
AT91SAM9G25-EK
Page of 1165
399
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
29.9.1.5  Null Pulse
Programming null pulse is not permitted. Pulse must be at least set to 1. A null value leads to unpredictable behavior.
29.9.2 Read Mode
As NCS and NRD waveforms are defined independently of one other, the SMC needs to know when the read data is 
available on the data bus. The SMC does not compare NCS and NRD timings to know which signal rises first. The 
READ_MODE parameter in the SMC_MODE register of the corresponding chip select indicates which signal of NRD and 
NCS controls the read operation.
29.9.2.1  Read is Controlled by NRD (READ_MODE = 1):
 shows the waveforms of a read operation of a typical asynchronous RAM. The read data is available t
PACC
 
after the falling edge of NRD, and turns to ‘Z’ after the rising edge of NRD. In this case, the READ_MODE must be set to 
1 (read is controlled by NRD), to indicate that data is available with the rising edge of NRD. The SMC samples the read 
data internally on the rising edge of Master Clock that generates the rising edge of NRD, whatever the programmed 
waveform of NCS may be.
Figure 29-10.READ_MODE = 1: Data is sampled by SMC before the rising edge of NRD
29.9.2.2  Read is Controlled by NCS (READ_MODE = 0)
PACC 
after the falling edge of the 
NCS signal and remains valid until the rising edge of NCS. Data must be sampled when NCS is raised. In that case, the 
READ_MODE must be set to 0 (read is controlled by NCS): the SMC internally samples the data on the rising edge of 
Master Clock that generates the rising edge of NCS, whatever the programmed waveform of NRD may be.
Data Sampling
t
PACC
MCK
A[25:2]
NBS0,NBS1,
NBS2,NBS3,
A0, A1
NCS
NRD
D[31:0]