Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
489
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
31.4.4 DMAC Transfer Types
A DMAC transfer may consist of single or multi-buffer transfers. On successive buffers of a multi-buffer transfer, the
DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods:
DMAC_SADDRx/DMAC_DADDRx registers in the DMAC are reprogrammed using either of the following methods:
Buffer chaining using linked lists
Replay mode
Contiguous address between buffers
On successive buffers of a multi-buffer transfer, the DMAC_CTRLAx and DMAC_CTRLBx registers in the DMAC are re-
programmed using either of the following methods:
programmed using either of the following methods:
Buffer chaining using linked lists
Replay mode
When buffer chaining using linked lists is the multi-buffer method of choice, and on successive buffers, the
DMAC_DSCRx register in the DMAC is re-programmed using the following method:
DMAC_DSCRx register in the DMAC is re-programmed using the following method:
Buffer chaining using linked lists
A buffer descriptor (LLI) consists of following registers, DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx,
DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set
up and describe the buffer transfer.
DMAC_CTRLAx, DMAC_CTRLBx.These registers, along with the DMAC_CFGx register, are used by the DMAC to set
up and describe the buffer transfer.
31.4.4.1 Multi-buffer Transfers
Buffer Chaining Using Linked Lists
In this case, the DMAC re-programs the channel registers prior to the start of each buffer by fetching the buffer descriptor
for that buffer from system memory. This is known as an LLI update.
for that buffer from system memory. This is known as an LLI update.
DMAC buffer chaining is supported by using a Descriptor Pointer register (DMAC_DSCRx) that stores the address in
memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor
(DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx).
memory of the next buffer descriptor. Each buffer descriptor contains the corresponding buffer descriptor
(DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx DMAC_CTRLBx).
To set up buffer chaining, a sequence of linked lists must be programmed in memory.
The DMAC_SADDRx, DMAC_DADDRx, DMAC_DSCRx, DMAC_CTRLAx and DMAC_CTRLBx registers are fetched
from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory
on buffer completion.
from system memory on an LLI update. The updated content of the DMAC_CTRLAx register is written back to memory
on buffer completion.
shows how to use chained linked lists in memory to define multi-buffer
transfers using buffer chaining.
The Linked List multi-buffer transfer is initiated by programming DMAC_DSCRx with DSCRx(0) (LLI(0) base address)
different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory.
different from zero. Other fields and registers are ignored and overwritten when the descriptor is retrieved from memory.
The last transfer descriptor must be written to memory with its next descriptor address set to 0.