Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
557
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
Figure 32-15.Data OUT Transfer for an Endpoint with Two Banks
32.6.10.13 High Bandwidth Isochronous Endpoint OUT
Figure 32-16.Bank Management, Example of Three Transactions per Microframe
USB 2.0 supports individual High Speed isochronous endpoints that require data rates up to 192 Mb/s (24 MB/s): 3x1024
data bytes per microframe.
data bytes per microframe.
To support such a rate, two or three banks may be used to buffer the three consecutive data packets. The microcontroller
(or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average).
(or the DMA) should be able to empty the banks very rapidly (at least 24 MB/s on average).
NB_TRANS field in UDPHS_EPTCFGx register = Number Of Transactions per Microframe.
If NB_TRANS > 1 then it is High Bandwidth.
Example:
If NB_TRANS = 3, the sequence should be either
MData0
MData0/Data1
MData0/Data1/Data2
Token OUT
ACK
Data OUT 3
Token OUT
Data OUT 2
Token OUT
Data OUT 1
Data OUT 1
Data OUT 2
Data OUT 2
ACK
Cleared by Firmware
USB Bus
Packets
Packets
Virtual RXRDY
Bank 0
Bank 0
Virtual RXRDY
Bank 1
Bank 1
Set by Hardware
Data Payload written
in FIFO endpoint bank 1
Data Payload written
in FIFO endpoint bank 1
FIFO (DPR)
Bank 0
Bank 0
Bank 1
Write by UDPHS Device
Write in progress
Read by Microcontroller
Read by Microcontroller
Set by Hardware,
Data payload written
in FIFO endpoint bank 0
Data payload written
in FIFO endpoint bank 0
Host sends first data payload
Microcontroller reads Data 1 in bank 0,
Host sends second data payload
Host sends second data payload
Microcontroller reads Data 2 in bank 1,
Host sends third data payload
Host sends third data payload
Cleared by Firmware
Write by Hardware
FIFO (DPR)
(UDPHS_EPTSTAx)
Interrupt pending
Interrupt pending
RXRDY = (virtual bank 0 | virtual bank 1)
Data OUT 1
Data OUT 3
MDATA0
MDATA0
MDATA1
DATA2
DATA2
MDATA1
t = 0
t = 52.5 µs
(40% of 125 µs)
(40% of 125 µs)
RXRDY
t = 125 µs
RXRDY
USB line
Read Bank 3
Read Bank 2
Read Bank 1
Read Bank 1
USB bus
Transactions
Transactions
Microcontroller FIFO
(DPR) Access
(DPR) Access