Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
675
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
35.5
Signal Description
35.6
Product Dependencies
35.6.1 I/O Lines
The pins used for interfacing the compliant external devices may be multiplexed with PIO lines. The programmer must
first program the PIO controllers to assign the SPI pins to their peripheral functions.
first program the PIO controllers to assign the SPI pins to their peripheral functions.
35.6.2 Power Management
The SPI may be clocked through the Power Management Controller (PMC), thus the programmer must first configure the
PMC to enable the SPI clock.
PMC to enable the SPI clock.
Table 35-1. Signal Description
Pin Name
Pin Description
Type
Master
Slave
MISO
Master In Slave Out
Input
Output
MOSI
Master Out Slave In
Output
Input
SPCK
Serial Clock
Output
Input
NPCS1-NPCS3
Peripheral Chip Selects
Output
Unused
NPCS0/NSS
Peripheral Chip Select/Slave Select
Output
Input
Table 35-2. I/O Lines
Instance
Signal
I/O Line
Peripheral
SPI0
SPI0_MISO
PA11
A
SPI0
SPI0_MOSI
PA12
A
SPI0
SPI0_NPCS0
PA14
A
SPI0
SPI0_NPCS1
PA7
B
SPI0
SPI0_NPCS2
PA1
B
SPI0
SPI0_NPCS3
PB3
B
SPI0
SPI0_SPCK
PA13
A
SPI1
SPI1_MISO
PA21
B
SPI1
SPI1_MOSI
PA22
B
SPI1
SPI1_NPCS0
PA8
B
SPI1
SPI1_NPCS1
PA0
B
SPI1
SPI1_NPCS2
PA31
B
SPI1
SPI1_NPCS3
PA30
B
SPI1
SPI1_SPCK
PA23
B