Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
818
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
39.7.1.2 Fractional Baud Rate in Asynchronous Mode
The Baud Rate generator previously defined is subject to the following limitation: the output frequency changes by only
integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator
that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is
only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula:
integer multiples of the reference frequency. An approach to this problem is to integrate a fractional N clock generator
that has a high resolution. The generator architecture is modified to obtain Baud Rate changes by a fraction of the
reference source clock. This fractional part is programmed with the FP field in the Baud Rate Generator Register
(US_BRGR). If FP is not 0, the fractional part is activated. The resolution is one eighth of the clock divider. This feature is
only available when using USART normal mode. The fractional Baud Rate is calculated using the following formula:
The modified architecture is presented below:
Figure 39-4. Fractional Baud Rate Generator
39.7.1.3 Baud Rate in Synchronous Mode or SPI Mode
If the USART is programmed to operate in synchronous mode, the selected clock is simply divided by the field CD in
US_BRGR.
US_BRGR.
In synchronous mode, if the external clock is selected (USCLKS = 3), the clock is provided directly by the signal on the
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 4.5 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the
receive part limits the SCK maximum frequency to MCK/4.5 in USART mode, or MCK/6 in SPI mode.
USART SCK pin. No division is active. The value written in US_BRGR has no effect. The external clock frequency must
be at least 4.5 times lower than the system clock. In synchronous mode master (USCLKS = 0 or 1, CLK0 set to 1), the
receive part limits the SCK maximum frequency to MCK/4.5 in USART mode, or MCK/6 in SPI mode.
When either the external clock SCK or the internal clock divided (MCK/DIV) is selected, the value programmed in CD
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
must be even if the user has to ensure a 50:50 mark/space ratio on the SCK pin. If the internal clock MCK is selected, the
Baud Rate Generator ensures a 50:50 duty cycle on the SCK pin, even if the value programmed in CD is odd.
Baudrate
SelectedClock
8 2
Over
–
(
) CD
FP
8
-------
+
----------------------------------------------------------------
=
MCK/DIV
16-bit Counter
0
Baud Rate
Clock
CD
CD
Sampling
Divider
0
1
>1
Sampling
Clock
Reserved
MCK
SCK
USCLKS
OVER
SCK
SYNC
SYNC
USCLKS = 3
1
0
2
3
0
1
0
1
FIDI
Glitch-free
Logic
Modulus
Control
FP
FP
BaudRate
SelectedClock
CD
--------------------------------------
=