Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

868

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

US_MR (SPI_MODE)

0xF801C004 (0), 0xF8020004 (1), 0xF8024004 (2), 0xF8028004 (3)

Read-write  

This configuration is relevant only if USART_MODE=0xE or 0xF in 

This register can only be written if the WPEN bit is cleared in 

– Applicable if USART operates in SPI Mode (USART_MODE = 0xE or 0xF):

CPHA = 0: Data is changed on the leading edge of SPCK and captured on the following edge of SPCK.

CPHA = 1: Data is captured on the leading edge of SPCK and changed on the following edge of SPCK.

CPHA determines which edge of SPCK causes data to change and which edge causes data to be captured. CPHA is used with 
CPOL to produce the required clock/data relationship between master and slave devices.

31

30

29

28

27

26

25

24

–

–

–

–

–

–

–

–

23

22

21

20

19

18

17

16

–

–

–

WRDBT

–

CPOL

15

14

13

12

11

10

9

8

–

–

–

–

–

–

–

CPHA

7

6

5

4

3

2

1

0

CHRL

USCLKS

USART_MODE

0xE

SPI_MASTER

SPI Master

0xF

SPI_SLAVE

SPI Slave

0

MCK

Master Clock MCK is selected

1

DIV

Internal Clock Divided MCK/DIV (DIV=8) is selected

3

SCK

Serial Clock SLK is selected

3

8_BIT

Character length is 8 bits