Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet
Product codes
AT91SAM9G25-EK
900
SAM9G25 [DATASHEET]
11032D–ATARM–10-Mar-2014
40.
Analog-to-Digital Converter (ADC)
40.1
Description
The ADC is based on a 10-bit Analog-to-Digital Converter (ADC) managed by an ADC Controller. Refer to the Block
Diagram:
Diagram:
. It also integrates a 12-to-1 analog multiplexer, making possible the analog-to-digital conversions
of 12
analog lines. The conversions extend from 0V to ADVREF. The ADC supports an 8-bit or 10-bit resolution mode,
and conversion results are reported in a common register for all channels, as well as in a channel-dedicated register.
Software trigger, external trigger on rising edge of the ADTRG pin or internal triggers from Timer Counter output(s) are
configurable.
configurable.
The comparison circuitry allows automatic detection of values below a threshold, higher than a threshold, in a given
range or outside the range, thresholds and ranges being fully configurable.
range or outside the range, thresholds and ranges being fully configurable.
The ADC also integrates a Sleep Mode and a conversion sequencer and connects with a DMA channel. These features
reduce both power consumption and processor intervention.
reduce both power consumption and processor intervention.
A whole set of reference voltages is generated internally from a single external reference voltage node that may be
equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.
equal to the analog supply voltage. An external decoupling capacitance is required for noise filtering.
Finally, the user can configure ADC timings, such as Startup Time and Tracking Time.
40.2
Embedded Characteristics
10-bit Resolution
440 kHz Conversion Rate
Wide Range Power Supply Operation
Integrated Multiplexer Offering Up to 12 Independent Analog Inputs
Individual Enable and Disable of Each Channel
Hardware or Software Trigger
External Trigger Pin
Internal Trigger Counter
DMA Support
Possibility of ADC Timings Configuration
Two Sleep Modes and Conversion Sequencer
Automatic Wakeup on Trigger and Back to Sleep Mode after Conversions of all Enabled Channels
Possibility of Customized Channel Sequence
Standby Mode for Fast Wakeup Time Response
Power Down Capability
Automatic Window Comparison of Converted Values
Write Protect Registers