Atmel Evaluation Kit AT91SAM9G25-EK AT91SAM9G25-EK Data Sheet

961

SAM9G25 [DATASHEET]

11032D–ATARM–10-Mar-2014

Note:

1.

STTDLY is set to 0. In this example, SSC_THR is loaded twice. FSDEN value has no effect on the transmis-
sion. SyncData cannot be output in continuous mode.

Note:

1.

STTDLY is set to 0.

The receiver can be programmed to receive transmissions from the transmitter. This is done by setting the Loop Mode 
(LOOP) bit in SSC_RFMR. In this case, RD is connected to TD, RF is connected to TF and RK is connected to TK.

Most bits in SSC_SR have a corresponding bit in interrupt management registers.

The SSC can be programmed to generate an interrupt when it detects an event. The interrupt is controlled by writing 
SSC_IER (Interrupt Enable Register) and SSC_IDR (Interrupt Disable Register) These registers enable and disable, 
respectively, the corresponding interrupt by setting and clearing the corresponding bit in SSC_IMR (Interrupt Mask 
Register), which controls the generation of interrupts by asserting the SSC interrupt line connected to the interrupt 
controller.

DATLEN

Data

DATLEN

Data

Default

Start 

From SSC_THR

From SSC_THR

TD

Start:  1. TXEMPTY set to 1 
           2. Write into the SSC_THR 

Data

DATLEN

Data

DATLEN

Start = Enable Receiver

To SSC_RHR

To SSC_RHR

RD